x86-64.net

Instruction

KXNORW

Computes the bitwise XNOR of two 16-bit masks.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KXNORW XORs the low 16 bits of two mask registers, inverts the result and writes it to a third, clearing bits 63:16: a bit is 1 where the two sources agree. It is part of AVX-512F; KXNORB needs AVX512DQ, and KXNORD and KXNORQ AVX512BW. KXORW describes the XOR and touches on the constant masks; this page is about the one compiled code mostly wants from KXNORW, all ones.

All ones from any register

A register agrees with itself everywhere, so KXNORW with the same source twice sets the low 16 bits whatever that register held: on Zen 5, kxnorw k7, k7, k7 turned 74870CD878C516B6H into FFFFH. Unlike a KMOVW of -1, it needs no general-purpose register. Gathers and scatters clear their mask as elements complete, so each needs a fresh one, and GCC 14 and Clang 23 at -O2 make it as follows.

  • Sixteen elements, as in _mm512_i32gather_epi32: GCC emits kxnorw k1, k1, k1, Clang kxnorw k1, k0, k0.
  • Eight, as in _mm512_i64gather_pd or _mm512_i64scatter_pd, with only -mavx512f: GCC moves -1 through EAX with KMOVW; Clang uses KXNORW, whose 16 ones cover the eight elements. With AVX512DQ, as in -march=x86-64-v4, both use KXNORB.
  • The AVX2 gathers take their mask in a vector register instead, which both compilers fill with ones by comparing a register with itself (GCC with VCMPPS, Clang with VPCMPEQD).

KXNORW still reads a register whose value does not matter, and neither vendor lists it among the idioms that break the dependency on that register, as the KXORW page explains.

Where two conditions agree

With two compare masks, KXNORW selects the elements where both conditions hold or both fail. For _mm512_kxnor of two compares GCC keeps KXNORW, while Clang inverts the second compare’s predicate (VPCMPLED for “not greater”) and uses KXORW, which gives the same mask. Written as ~(m1 ^ m2) and used as the mask of an add, it became KXNORW in both. AMD’s Zen 5 guide lists KXNORW as one macro-op with a latency of one cycle.

Forms

Every encoding of KXNORW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KXNORW k, k, k KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W0 46 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = ~(k2.w[0] ^ k3.w[0])   # 1 where the bits agree: all ones
                                 # when k2 and k3 are one register
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KXNORW k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KXNORW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_kxnor __mmask16 _mm512_kxnor(__mmask16 __A, __mmask16 __B)

KXNORW k, k, k VEX.L1 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-530 (KXNORW/KXNORB/KXNORQ/KXNORD)
  7. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.