x86-64.net

Instruction

KXORW

Computes the bitwise XOR of two 16-bit masks.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KXORW XORs the low 16 bits of two mask registers into a third and clears bits 63:16 of the result. It is part of AVX-512F, with KXNORW, which inverts the XOR; KXORB needs AVX512DQ, and KXORD and KXORQ AVX512BW.

Elements where two conditions differ

The XOR of two compare masks selects the elements where exactly one condition holds. GCC 14 and Clang 23 at -O2 and -mavx512f compile such a mask, used for a masked add, to two compares and a KXORW.

XORed with a shifted copy of itself, a mask marks where its bits change. m ^ (m << 1) on a compare result became KSHIFTLW and KXORW in both compilers. Intel’s optimization manual uses KSHIFT and KXOR the same way in its top-k search (Example 8-14), where the compare yields a run of ones: the XOR with its shifted copy keeps one bit at each edge of the run, and those bits select the elements that a blend then replaces.

Constant masks

A register XORed with itself gives zero, and XNORed with itself all ones, whatever it held. The all-ones form is the one compiled code needs: a gather clears its mask as elements arrive, so every VPGATHERDD needs a fresh full mask. For _mm512_i32gather_epi32 GCC emits kxnorw k1, k1, k1 and Clang kxnorw k1, k0, k0 before the gather, as Intel’s manual does before the gathers and scatters of its histogram example (Example 17-24). A zero mask is rarely needed, since an unmasked instruction needs none.

The instruction table of AMD’s Zen 5 guide lists KXORW as one macro-op with a latency of one cycle. Neither vendor’s list of dependency-breaking idioms names a mask instruction (Intel’s optimization manual, Section 3.5.1.7; AMD’s Zen 5 guide, Section 2.9.2), so nothing promises that KXORW or KXNORW of a register with itself skips waiting for that register’s old value, as XOR of a general-purpose register does.

Forms

Every encoding of KXORW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KXORW k, k, k KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W0 47 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = k2.w[0] ^ k3.w[0]
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KXORW k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KXORW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_kxor __mmask16 _mm512_kxor(__mmask16 __A, __mmask16 __B)

KXORW k, k, k VEX.L1 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-531 (KXORW/KXORB/KXORQ/KXORD)
  7. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.