LAHF instruction (LAHF-SAHF)

LAHF copies the low byte of the flags register into AH: SF, ZF, AF, PF and CF in bits 7, 6, 4, 2 and 0, with bit 1 reading 1 and bits 3 and 5 reading 0. Nothing else changes, the flags included. Its partner SAHF writes those five flags back from AH. Together they save and restore the arithmetic flags in a register, without the stack that PUSHF and POPF need.

OF is missing

OF lives in bit 11, outside the byte that LAHF copies, so code that must keep all six arithmetic flags saves OF separately. One way:

save with lahf and seto al;
restore with add al, 0x7f, which sets OF exactly when AL is 1, since 1 + 0x7F overflows a signed byte and 0 + 0x7F does not, and then sahf, which rewrites the other five flags and leaves OF alone.

64-bit mode

In 64-bit mode, both vendors’ manuals make LAHF and SAHF depend on a CPUID bit, CPUID.80000001H:ECX[0], and raise #UD without it; in the other modes, compatibility mode included, they always work. The bit is part of x86-64-v2, not of the baseline, and Linux shows it as lahf_lm. This site’s Zen 5 reports it and ran the instruction in 64-bit mode.

In compiled code

In the code we built with GCC 14 and Clang 23 at -O2, neither emitted LAHF; to keep a single flag, both use SETcc. SAHF still appears in x87 code for processors before the P6 family, which introduced FCOMI: Clang compiles a < b on long double with -m32 -march=i486 to FUCOMPP, FNSTSW AX and SAHF, which moves the x87 condition codes into the flags for SETA. GCC, for the same target, tests AH directly.

The instruction table of AMD’s Zen 5 guide lists LAHF as one macro-op with a latency of one cycle, while PUSHF and POPF are microcoded.

Forms

Every encoding of LAHF that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LAHF` LAHF	`9F`	LAHF

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`LAHF`
Sandy Bridge	1 / 0.5p05
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.5p06
Alder Lake, Sapphire Rapids	3 / 0.5p06
Bonnell	2 / 1p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	2 / 2EX0 EX1
Zen, Zen 2	100 / 0.25
Zen 3, Zen 4	1 / 1ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = sf << 7 | zf << 6 | af << 4
ah = v | pf << 2 | 2 | cf        # bit 1 reads 1, bits 3 and 5 read 0
# in 64-bit mode, only on a processor with CPUID.80000001H:ECX[0]
# (LAHF-SAHF); #UD otherwise

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LAHF`
`AH`	implicit	write
`RFLAGS`	implicit	read

Flags

T tested; blank: not affected. How to read.

SF	ZF	AF	PF	CF
All forms
T	T	T	T	T

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`LAHF` LAHF-SAHF	LAHF `CPUID.80000001H:ECX[0]` LAHF	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More LAHF-SAHF instructions

SAHF

OF is missing#

64-bit mode#

In compiled code#