LAR instruction (System)

Forms

Every encoding of LAR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LAR r16/32/64, m16` LAR_GPRv_MEMw	`0F 02 /r`	Base instruction set
`LAR r16/32/64, r16/32/64` LAR_GPRv_GPRv	`0F 02 /r`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

sel = src.read() & 0xFFFF        # bits 15:0 of a register count
ok = 0
if sel & 0xFFFC and in_table(sel):
    d = descriptor(sel)          # not null, and within its table
    t = d >> 40 & 0xF            # the type
    if d >> 44 & 1:              # S: a code or data segment, any
        ok = 1
    elif t in (2, 9, 0xB, 0xC):  # LDT, TSS, call gate: 16 bytes
        if in_table(sel + 8):
            hi = descriptor(sel + 8)
            ok = hi >> 40 & 0x1F == 0
    dpl = d >> 45 & 3
    if not (d >> 44 & 1 and t & 0xC == 0xC):
        if CPL > dpl or sel & 3 > dpl:
            ok = 0               # not visible: conforming code alone
                                 # is visible from any level
if ok:
    r = d >> 32 & 0xFFFF00       # bits 23:8 of the second dword
    if OSIZE == 16:
        r = r & 0xFF00           # type, S, DPL and P; bits 63:16 kept
    dest.write(r)                # 32 and 64: AVL, L, D/B and G too,
                                 # zero-extended
zf = ok
# bits 19:16 hold the limit's bits 19:16 (AMD's manual and Zen 5);
# Intel's manual leaves them undefined. The check of the second
# entry is in AMD's manual for LAR, in both for LSL

Run on AMD Zen 5 (EPYC 9645): 35 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LAR r16/32/64, m16`
`r16/32/64`	explicit	conditional write
`m16`	explicit	read
`RFLAGS`	implicit	write
`LAR r16/32/64, r16/32/64`
`r16/32/64`	explicit	conditional write
`r16/32/64`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified; blank: not affected. How to read.

ZF
All forms
M

Attributes

What else XED records about the forms. How to read.

All forms: not in real-address mode

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I286PROTECTED` System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

LAR