LDDQU

LDDQU loads 16 bytes from any address into an XMM register, as MOVDQU does, and keeps bits 128 and up of the register; its VEX form, VLDDQU, loads 16 or 32 bytes and zeroes the rest. It came with SSE3 as a load for data that crosses a cache line: instead of the exact bytes, the processor may read the two aligned blocks around them and pick the requested bytes out. Intel’s volume 1 describes that as reading 32 bytes from the 16-byte boundary below the address; AMD’s manual allows it and also allows reading exactly the bytes requested.

Where it is the wrong load#

Since the reads may cover more bytes than requested, or the same bytes more than once, the manuals advise MOVDQU, or AMD’s MOVUPD, instead in some places:

• memory that is uncached or write-combining, such as a device’s registers or a frame buffer, where an extra or repeated read can have effects or be slow;
• data that the program loads, changes and stores back to the same place, and loads that should be forwarded from a recent store (Intel’s instruction reference);
• code that relies on the 16 bytes being read at once: Intel’s reference warns that some processors split the load into several reads, which another thread’s store can fall between.

Like MOVDQU, it never faults for a misaligned address; whether #AC applies to it depends on the processor.

In practice#

Intel’s optimization manual notes that already the Core Solo and Core Duo treated LDDQU as an ordinary 16-byte load. AMD’s Zen 5 guide lists LDDQU and VLDDQU as single macro-ops. Compilers emit LDDQU only where the program asks for it: GCC 14 and Clang 23 at -O2 compile _mm_lddqu_si128 to LDDQU (it needs -msse3), and with -mavx2 to VLDDQU, but they did not fold it into an arithmetic instruction’s memory operand, as they fold _mm_loadu_si128 into vpaddd xmm0, xmm0, xmmword ptr [rdi]. The case recorded on Zen 5 loaded 16 bytes from an aligned address and left the upper half of YMM1 as it was.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(mem.read())
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to LDDQU, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPD
• ADDSUBPS
• FISTTP
• HADDPD
• HADDPS
• HSUBPD
• HSUBPS
• MOVDDUP
• MOVSHDUP
• MOVSLDUP