LDMXCSR instruction (SSE)

LDMXCSR loads MXCSR, the control and status register of the SSE, AVX and AVX-512 floating-point instructions, from a doubleword in memory. STMXCSR stores it, and the pair is how code changes a part of it: store, edit the bits, load. MXCSR holds:

bits 5:0, the sticky exception flags (invalid, denormal, divide by zero, overflow, underflow, precision);
bits 12:7, their masks, set by default;
bits 14:13, the rounding mode;
bit 6, DAZ, which reads denormal inputs as zero, and bit 15, FTZ, which flushes denormal results to zero.

Its value after reset is 1F80H: all exceptions masked, flags clear, round to nearest. VLDMXCSR is the VEX form, with the same effect.

From C

_mm_setcsr(v) compiles in GCC 14 and Clang 23 at -O2 to a store of the value to the stack and an LDMXCSR from there, and _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON) to STMXCSR, an OR of 8000H and LDMXCSR; with -mavx both become VSTMXCSR and VLDMXCSR. Standard C’s fesetround stays a call into the library.

Reserved bits

A set bit that MXCSR_MASK does not allow raises #GP(0), and nothing is loaded. Software reads the mask from bytes 28 to 31 of an FXSAVE image; Intel’s Volume 1 says that 0 there means FFBFH. Zen 5’s is 2FFFFH: it loaded FFFFH and 2FFFFH, bit 17 being AMD’s misaligned-exception mask (MM), and raised #GP for 11F80H and 80001F80H, leaving MXCSR as it was. AND a value with the mask before loading it to stay safe on any processor.

No exception on the spot

LDMXCSR raises no floating-point exception itself, even when it unmasks an exception whose flag is already set. Intel’s manual says that the exception comes only from the next SSE or AVX instruction that reports that condition; the flag alone does not raise it. Zen 5 loaded 0, which unmasks every exception, without a fault.

Cost

Intel’s optimization manual says a write to MXCSR is serializing and advises against changing it often; CVTTSS2SI truncates without touching the rounding mode, and AVX-512’s embedded rounding sets it per instruction (Sections 3.9.3, 7.5.2 and 17.10.1). AMD’s Zen 5 guide recommends setting DAZ and FTZ where denormal precision is not needed, to avoid the slow paths of multiply, divide and square root (Sections 2.11.2 and 2.11.4).

In the optimization guide

What the optimization guide says about LDMXCSR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

Denormals, FTZ and DAZ: Writing MXCSR with LDMXCSR serializes the processor and reading it is slow, so FTZ and DAZ are best set once.

Forms

Every encoding of LDMXCSR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LDMXCSR m32` LDMXCSR_MEMd	`NP 0F AE /2`	SSE

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = src.read()
if v & ~mxcsr_mask:                  # a bit the processor does not have
    fault(GP, 0)
mxcsr = v                            # a flag set with its mask clear
                                     # raises nothing here, nor later:
                                     # an instruction raises only what
                                     # it reports itself

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LDMXCSR m32`
`m32`	explicit	read
`MXCSR`	implicit	write

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSEMXCSR` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

From C#

Reserved bits#

No exception on the spot#

Cost#