x86-64.net

Instruction

LDTILECFG

Loads the AMX tile configuration (palette, rows and bytes per row of each tile) from a 64-byte memory block and zeroes the tile registers.

Extensions
Forms
2 (1 VEX, 1 EVEX)
Data
Intel XED v2026.08.23

LDTILECFG reads a 64-byte block that selects a palette and, for palette 1, gives the shape of every tile:

BytesField
0palette: 0 releases the tiles, 1 is AMX, 2 is ACE
1start_row, used to resume an interrupted tile load or store; normally 0
2-15reserved, zero
16-31bytes per row of tiles 0 to 7, two bytes each
32-47reserved, zero
48-55rows of tiles 0 to 7, one byte each
56-63reserved, zero

Unused tiles must have zero in both fields. A palette the processor does not support, a shape beyond its limits or a nonzero reserved byte raises #GP. Loading a configuration also clears all tile data, so a program configures once and then works with the tiles; ACE’s palette 2 has fixed tile shapes and uses only byte 0. STTILECFG writes the current configuration back in the same format.

Forms

Every encoding of LDTILECFG that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
LDTILECFG m512 64-bit mode only LDTILECFG_MEMVEX.LZ.NP.0F38.W0 49 /0ACE v1 or AMX_TILE
LDTILECFG m512 LDTILECFG_MEM_APXEVEX.LLZ.NP.0F38.W0 49 /0ACE v1 or APX_F + AMX_TILE

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to LDTILECFG, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_tile_loadconfig void _tile_loadconfig(const void *__config)

LDTILECFG m512 VEX.LZ -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_TILE_BASE

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
APX_F_AMX_BASE

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

APX_F + AMX_TILE
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Diamond Rapids

More AMX-TILE instructions

More ACE instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.