LES instruction (General-purpose)

LES loads a far pointer from memory: the offset into a general-purpose register and the 16-bit selector after it into ES, m16:32 at the 32-bit operand size and m16:16 at the 16-bit one. Everything else is as for LDS: the descriptor check of a MOV to ES in protected mode, a null selector accepted until ES is used, and a plain load in real mode. ES is the segment of the destination of the string instructions, such as MOVS and STOS, so LES and LDS together set up a copy between two segments. LFS shows the same load on Zen 5 for FS, which 64-bit mode kept.

C4 became VEX

C4 with a ModRM byte of mod = 11b was never a valid LES, and the three-byte VEX prefix uses those bytes in 32-bit code. Intel’s manual says that the bits after C4 that hold VEX.R and VEX.X, inverted, must both be 1 there, otherwise the instruction is LES. Both select registers 8 to 15, which 32-bit code does not have. In 64-bit mode C4 always starts a VEX prefix, and LES does not exist.

Not in 64-bit mode

The fixture has no case for LES: the probe runs in 64-bit mode, where C4 starts a VEX instruction, and lists the form as not run. GNU as 2.44 and Clang 23 refuse les in 64-bit code. AMD’s Zen 5 guide lists LES as microcoded, without a latency.

Forms

Every encoding of LES that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LES r16/32, m16:16/32` not in 64-bit mode LES_GPRz_MEMp	`C4 /r`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = src.read()                   # m16:16 or m16:32
load_segment(es, v >> OSIZE)     # checks the descriptor it names
dest.write(v)                    # the offset: the low OSIZE bits

Not run on a processor: LES does not exist in 64-bit mode, where the probe runs: C4 starts a VEX prefix there.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LES r16/32, m16:16/32` not in 64-bit mode
`r16/32`	explicit	write
`m16:16/32`	explicit	read
`ES`	implicit	write

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

C4 became VEX#

Not in 64-bit mode#