LGS instruction (General-purpose)

LGS loads a far pointer from memory, an offset and then a 16-bit selector, into a general register and GS. It is LFS with GS for FS, opcode 0F B5 for 0F B4, and that page covers the pointer’s sizes, the checks of the selector and the REX.W form, where Intel’s manual reads an 80-bit pointer and AMD’s supports none; Zen 5 read 48 bits. Zen 5 recorded the same results for LGS as for LFS: the same selectors loaded and the same four raised #GP.

The active base only

A selector load takes GS’s base from the descriptor, 32 bits with bits 63:32 cleared. Zen 5, given random 64-bit bases, had a GS base of 0 after LGS loaded 2Bh, Linux’s user data segment, and the FS base unchanged. In 64-bit mode two GS bases exist: the active one and the IA32_KERNEL_GS_BASE MSR, which SWAPGS exchanges on the way into the kernel and out. LGS, like MOV to GS, writes only the active one. Intel added LKGS for the other: it checks a selector the same way but puts the descriptor’s base in IA32_KERNEL_GS_BASE; it came with FRED, which makes the swap itself.

In user space

Linux’s documentation leaves GS to the program, where FS belongs to the threading library, and gives WRGSBASE and arch_prctl(ARCH_SET_GS, ...) to set its base; an LGS replaces it with a descriptor’s base, 0 for 2Bh. GCC 14 and Clang 23 do not use LGS for their __seg_gs address space: they put a GS prefix on the access, mov eax, dword ptr gs:[rdi+0xc], and leave the base to whoever set it.

Forms

Every encoding of LGS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LGS r16/32/64, m16:16/32/64` LGS_GPRv_MEMp2	`0F B5 /r`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r16, m16:16/32/64` `r32, m16:16/32/64` `r64, m16:16/32/64`
Sandy Bridge	100 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids	100 / 0.25p0156
Lunar Lake	100 / 0.17p012345
Bonnell	100 / 0.5p1
Silvermont	100 / 1FPC0
Piledriver	100 / 0.5EX0 EX1
Zen, Zen 2	100 / 0.25
Zen 3, Zen 4	100 / 25ALU0 ALU1 ALU2 ALU3
Jaguar	100 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = OSIZE                        # the offset's size
if OSIZE == 64:                  # REX.W: m16:64 on Intel's (SDM
                                 # Volume 2A, LDS/LES/LFS/LGS/LSS,
                                 # rev. 093)
    if AMD:
        n = 32                   # no m16:64, but m16:32 (APM Volume
                                 # 3, LFS and Table B-1, rev. 3.36;
                                 # Zen 5)
off = load(src.address, n)       # the offset, then the selector
sel = load(src.address + n // 8, 16)
load_segment(gs, sel)            # checks the descriptor it names,
                                 # whose base GS takes
dest.write(off)                  # REX.W on AMD's: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 18 cases. Its branches for Intel's processors were not run: no Intel processor ran these forms.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LGS r16/32/64, m16:16/32/64`
`r16/32/64`	explicit	write
`m16:16/32/64`	explicit	read
`GS`	implicit	write

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

The active base only#

In user space#