LIDT

LIDT loads IDTR, the register that tells the processor where the interrupt descriptor table lies, from a pseudo-descriptor in memory: the 16-bit limit, then the base, 8 bytes of it in 64-bit mode, so 10 in all. It is the twin of LGDT, whose page covers what the two share: the operand sizes outside 64-bit mode, with the 24-bit base of a 16-bit operand size, and #GP(0) for a non-canonical base. SIDT stores the register.

The table it points to#

The IDT holds one gate per vector, 0 to 255, and the processor finds a vector’s gate at base + vector times the gate size. In 64-bit mode every gate is 16 bytes, to hold a 64-bit handler address, so a table of all 256 vectors has the limit 4095 (FFFH); in protected mode gates are 8 bytes. The limit is inclusive, and a table may stop short: a vector whose gate lies past the limit raises #GP when it arrives. Unlike the GDT, entry 0 is used: it is the gate of #DE, the divide error.

When it runs#

An operating system runs LIDT during start-up, after it has built the table, and may run it again to move to another one. After reset IDTR holds base 0 and limit FFFFH, which covers real mode’s table of 4-byte vectors at address 0. LIDT reads only its operand: as with LGDT, a bad gate shows up only when its vector is delivered. With Intel’s FRED enabled, events no longer go through the IDT at all.

Privilege and order#

LIDT runs only at CPL 0; elsewhere it raises #GP(0). At CPL 3, Zen 5 raised #GP in both recorded cases, leaving memory and RFLAGS alone. LIDT m16&32 does not exist in 64-bit mode, where the probe runs, so it was not run. Both vendors list LIDT as serializing, and under VMX a hypervisor can make it exit with descriptor-table exiting. Neither GCC 14 nor Clang 23 has an intrinsic for it. AMD’s Zen 5 guide lists LIDT as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
v = src.read()                   # 10 bytes: the limit, then the base
if not canonical(v >> 16):
    fault(GP, 0)
idtr = v                         # the limit in bits 15:0, the base in
                                 # bits 79:16, as SIDT stores them

if CPL > 0:
    fault(GP, 0)
v = src.read()                   # 6 bytes: the limit, then the base
b = v >> 16                      # 32 bits; with a 66 prefix the low
if OSIZE == 16:                  # 24, the top byte unused
    b &= 0xFFFFFF
idtr = b << 16 | v & 0xFFFF

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More System instructions

• ARPL
• CLTS
• HLT
• INVD
• INVLPG
• LAR
• LGDT
• LLDT
• LMSW
• LSL
• LTR
• RDMSR
• RDPMC
• RDTSC
• RSM
• SGDT
• SIDT
• SLDT
• SMSW
• STR
• SWAPGS
• VERR
• VERW
• WBINVD
• WRMSR