x86-64.net

Instruction

LKGS

Loads GS from a selector but puts the descriptor's base in the IA32_KERNEL_GS_BASE MSR instead of the GS base; ring 0 of 64-bit mode only.

Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of LKGS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
LKGS r16 64-bit mode only LKGS_GPR16u16F2 0F 00 /6LKGS
LKGS m16 64-bit mode only LKGS_MEMu16F2 0F 00 /6LKGS

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
LKGS

LKGS
CPUID.(EAX=07H,ECX=1):EAX[18] LKGS

Panther Lake, Nova Lake, Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Flexible Return and Event Delivery (FRED) Specification (346446-009)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.