LLWPCB instruction (LWP)

Forms

Every encoding of LLWPCB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LLWPCB r32/64` LLWPCB_GPRyy	`XOP.LZ.NP.09.WIG 12 /0`	LWP

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r32/64`
Piledriver	100 / 0.5EX0 EX1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 15 & 1:
    fault(UD)                    # CPUID: no LWP
if not xcr0 >> 62 & 1:           # LWP's state not enabled by the
    fault(UD)                    # OS
e = cpuid_leaf(0x8000001C, 0)    # LWP's layout: where the events
off = e[1] >> 24                 # start in an LWPCB, how many
n = e[1] >> 16 & 0xFF            # there are, and the least ring
least = 1024 * (e[2] >> 16 & 0xFF)  # buffer, in bytes
old = lwp_cbaddr
if old:                          # running: its state goes to the
    opts = load(old, 32)         # LWPCB in use first, as SLWPCB
    for i in range(1, n + 1):    # stores it
        if opts >> i & 1:
            at = old + off + 8 * i - 4
            c = lwp_count[i] & 0x3FFFFFF
            store(at, 32, c)     # EventCounter i
    store(old + 16, 32, lwp_head)
a = src.read()                   # the new LWPCB's address
if a == 0:
    lwp_cbaddr = 0               # LWP off
else:
    size = load(a + 4, 32) & 0xFFFFFFF
    size -= size % 32            # whole records of 32 bytes
    if size < least:             # LWP is left off (the APM)
        fault(GP, 0)
    opts = load(a, 32) & lwp_cfg
    opts &= 0xE000007E           # what is on, as the OS allows
    store(a, 32, opts)           # it, written back
    for i in range(1, n + 1):    # each event that is on: its
        if opts >> i & 1:        # interval and its counter, signed
            at = a + off + 8 * i - 8  # numbers of 26 bits
            v = load(at, 32) & 0x3FFFFFF
            if v >> 25:
                v -= 1 << 26
            v = max(v, lwp_min(i))  # not below the processor's
            store(at, 32, v)     # least, nor 0 (LWPVAL's)
            c = load(at + 4, 32) & 0x3FFFFFF
            if c >> 25:
                c -= 1 << 26
            lwp_count[i] = max(c, 0)
    h = load(a + 16, 32)         # the head: in the buffer, and on
    h -= h % 32                  # a record's boundary
    lwp_head = 0 if h >= size else h
    lwp_cbaddr = a               # LWP on
# the addresses are DS's offsets, its base 0 in 64-bit mode, and
# LWP keeps them as linear addresses. A fault on the old LWPCB
# leaves LWP running with it; one from the new LWPCB leaves it off.
# XED lists src as written: the APM has LLWPCB only read it

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no LWP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LLWPCB r32/64`
`r32/64`	explicit	write

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to LLWPCB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`__llwpcb` `void __llwpcb(void *__addr)`	`LLWPCB r32/64` XOP.LZ -mlwp

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`LWP` LWP	LWP `CPUID.80000001H:ECX[15]` LWP	Bulldozer, Piledriver

LLWPCB