Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of LOADIWKEY that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
LOADIWKEY xmm, xmm LOADIWKEY_XMMu8_XMMu8F3 0F 38 DC /rKL + KLENABLED

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm
Alder Lake100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 19 & 1:            # CR4.KL; clear without Key Locker
    fault(UD)
if cr0 >> 2 & 1 or not cr4 >> 9 & 1:
    fault(UD)                    # CR0.EM set, CR4.OSFXSR clear
if cr0 >> 3 & 1:
    fault(NM)                    # CR0.TS
if CPL > 0:
    fault(GP, 0)
c = eax                          # bit 0 NoBackup, 4:1 KeySource
ks = c >> 1 & 0xF
has = cpuid_leaf(0x19, 0)[2]     # bit 0: NoBackup; 1: KeySource 1
if ks > 1 or c >> 5:
    fault(GP, 0)                 # reserved
if c & 1 and not has & 1:
    fault(GP, 0)
if ks == 1 and not has >> 1 & 1:
    fault(GP, 0)
k = xmm[0] << 256 | src1 << 128 | src2
                                 # the integrity key, from XMM0, and
                                 # the encryption key, from the two
ok = 1
if ks == 1:                      # KeySource 1: mixed with random
    ok = seed_ready()            # bits of RDSEED's source, so that
    if ok:                       # not even CPL 0 knows the key
        k = k ^ seed(384)
if ok:
    iwkey = k | (c & 0x1F) << 384
zf = 1 - ok                      # no random bits ready: IWKey kept
of = sf = af = pf = cf = 0

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no Key Locker, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
LOADIWKEY xmm, xmm
xmmexplicitread
xmmexplicitread
EAXimplicitread
XMM0implicitread
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
00M000

Attributes

What else XED records about the forms. How to read.

All forms
privileged: CPL 0 only

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to LOADIWKEY, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_loadiwkey void _mm_loadiwkey(unsigned int __ctl, __m128i __intkey, __m128i __enkey_lo, __m128i __enkey_hi)

LOADIWKEY xmm, xmm Legacy -mkl

LOADIWKEY xmm, xmm Legacy -mkl -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
KEYLOCKER

KL + KLENABLED
CPUID.(EAX=07H,ECX=0):ECX[23] KL
CPUID.(EAX=19H,ECX=0):EBX[0] KLENABLED

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sierra Forest, Clearwater Forest

More Key Locker instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-562 (LOADIWKEY)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.