x86-64.net

Instruction

LODS

Loads the element at [RSI] into AL, AX, EAX or RAX and steps RSI up or down, as the direction flag says.

Extensions
Mnemonics
LODS, LODSB, LODSW, LODSD, LODSQ
Forms
8 (8 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of LODS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
LODSB LODSBACBase instruction set
LODSW LODSW66 ADBase instruction set
LODSD LODSDADBase instruction set
LODSQ 64-bit mode only LODSQREX.W ADLM
REP LODSB REP_LODSBF3 AC
F2 AC		Base instruction set
REP LODSW REP_LODSW66 F3 AD
66 F2 AD		Base instruction set
REP LODSD REP_LODSDF3 AD
F2 AD		Base instruction set
REP LODSQ 64-bit mode only REP_LODSQF3 REX.W AD
F2 REX.W AD		LM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.