Extensions
Mnemonics
LODS, LODSB, LODSW, LODSD, LODSQ
Forms
8 (8 Legacy)
Data
Intel XED v2026.08.23

LODS loads the element at [RSI] into AL, AX, EAX or RAX and moves RSI to the next one, up or down as the direction flag says. It is the reading half of a hand-written string loop: lodsb, some work on AL, then stosb to store the result at [RDI], one byte each, which keeps such code short. Compiled code reads bytes with MOVZX instead: GCC 14 at -O2 compiles a byte-by-byte copy loop to movzx ecx, byte ptr [rsi + rax] and a byte MOV, stepping a single index.

The register it writes

LODSD writes EAX and therefore clears bits 63:32 of RAX, like any 32-bit write. LODSB and LODSW replace only AL or AX and keep the rest of RAX, so a loop that uses all of RAX afterwards must clear it first, or widen AL with MOVZX.

REP LODS

Both manuals accept a REP prefix, but each element overwrites the one before, so REP LODS leaves only the last element in rAX, with RSI past the end and RCX at 0; with RCX = 0 it leaves rAX alone. Zen 5 ran it exactly so, and the same with F2 for a count of 3. It does little that a single load and an ADD to RSI would not.

The source segment

The source may take a segment prefix. In 64-bit mode only FS and GS add a base, so lods eax, dword ptr fs:[rsi] reads RSI bytes past the base of FS, which the psABI makes the thread pointer (see thread-local storage). STOS, its partner, cannot be redirected: it always writes through ES:RDI.

Speed

The instruction table that comes with AMD’s Zen 5 guide lists LODSB, like the other string instructions, as microcoded, where a MOVZX from memory is a single macro-op. The direction flag, the resumption after a fault and the 67 prefix work as on the MOVS page.

Forms

Every encoding of LODS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
LODSB LODSBACBase instruction set
LODSW LODSW66 ADBase instruction set
LODSD LODSDADBase instruction set
LODSQ 64-bit mode only LODSQREX.W ADLM
REP LODSB REP_LODSBF3 AC
F2 AC
Base instruction set
REP LODSW REP_LODSW66 F3 AD
66 F2 AD
Base instruction set
REP LODSD REP_LODSDF3 AD
F2 AD
Base instruction set
REP LODSQ 64-bit mode only REP_LODSQF3 REX.W AD
F2 REX.W AD
LM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelLODSB
LODSW
LODSB
LODSW
LODSD
LODSQ
LODSD
LODSQ
Sandy Bridge7 / 0.67p0 p1 p5 p236 / 0.5p0 p1 p5 p23
Haswell1 / 0.5p0123561 / 0.5p012356
Broadwell, Skylake, Skylake-SP, Ice Lake100 / 0.25p0156100 / 0.25p0156
Alder Lake, Sapphire Rapids6 / 0.6p0 p1 p2 p3 p5 p6 p10 p115 / 0.4p0 p1 p2 p3 p5 p6 p10 p11
Lunar Lake100 / 0.17p012345100 / 0.17p012345
Bonnell2 / 1p012 / 1p01
Silvermont100 / 1FPC0100 / 1FPC0
Piledriver100 / 0.5EX0 EX1100 / 0.5EX0 EX1
Zen, Zen 2100 / 0.25100 / 0.25
Zen 3, Zen 4100 / 25ALU0 ALU1 ALU2 ALU3100 / 25ALU0 ALU1 ALU2 ALU3
Jaguar100 / 0.5ALU0 ALU1100 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the REP forms
step = -(OSIZE // 8) if df else OSIZE // 8
rAX = load(aSI, OSIZE)           # EAX: bits 63:32 cleared
aSI = low(aSI + step, ASIZE)

Run on AMD Zen 5 (EPYC 9645): 16 cases.

REP forms
step = -(OSIZE // 8) if df else OSIZE // 8
s = aSI
for i in range(aCX):
    rAX = load(s, OSIZE)         # the last element stays; with aCX 0,
    s = low(s + step, ASIZE)     # rAX is left alone
aSI = s
aCX = 0

Run on AMD Zen 5 (EPYC 9645): 24 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
LODSB LODSW LODSD LODSQ 64-bit mode only
AL, AX, EAX, RAXimplicitwrite
m8/16/32/64 at [rSI]implicitread
rSIimplicitread, write
RFLAGSimplicitread
REP LODSB REP LODSW REP LODSD REP LODSQ 64-bit mode only
AL, AX, EAX, RAXimplicitconditional write
m8/16/32/64 at [rSI]implicitconditional read
rSIimplicitread, conditional write
rCXimplicitread, conditional write
RFLAGSimplicitread

Flags

T tested; blank: not affected. How to read.
DF
All forms
T

Attributes

What else XED records about the forms. How to read.

REP forms
repeated: count in rCX

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-567 (LODS/LODSB/LODSW/LODSD/LODSQ)
  5. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
  6. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.