LOOPNE instruction (General-purpose)

LOOPNE (also LOOPNZ, E0 cb) works like LOOP: it subtracts 1 from RCX, ECX with a 67 prefix, without touching the flags, and jumps to a short relative target while the count is not zero, but only if ZF is also 0. With a CMP in the loop body, it searches: the loop runs while the compares fail and stops at the first match or when the count runs out. LOOPE is the opposite test, and LOOP’s page covers the counter’s size, a count of 0 and why compilers avoid the family.

Found or not

LOOPNE leaves the flags alone, so after the loop ZF = 1 means the last compare matched and ZF = 0 that the count ran out without a match. That is the counted search that repne scasb performs in one instruction, as the SCAS page describes, with any compare in the body: a byte in a range, a field of a structure.

On Zen 5

With RCX = 2 and ZF = 0 it jumped back and left RCX = 1; with ZF = 1 it fell through, though RCX was decremented all the same.
With RCX = 0 and ZF = 0 it wrapped RCX to 2^64 - 1 and jumped.
RCX = 2^32 became 2^32 - 1 with no jump when ZF was 1. With a 67 prefix, ECX = 1 in a register whose upper half was nonzero became RCX = 0, the whole register, and the loop ended.

Neither GCC 14 nor Clang 23 emits it in our builds, at -O2 or at -Os, not even for a search loop. AMD’s Zen 5 guide lists LOOPNE as microcoded, like LOOP.

Forms

Every encoding of LOOPNE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`LOOPNE rel8` LOOPNE_RELBRb	`E0 cb`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`rel8`
Sandy Bridge	4 / 4p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	11 / 2.75p0156
Alder Lake, Sapphire Rapids	2 / 3p0 p1 p5 p6 p11
Lunar Lake	2 / 2p012345
Bonnell	17 / 8.5p01
Silvermont	1 / 1IEC1
Piledriver	1 / 1Branch EX1
Zen, Zen 2	1 / 0.5ALU0 ALU3
Zen 3, Zen 4	1 / 0.5ALU0 BRU1
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

w = OSIZE                        # as LOOP's
if OSIZE == 16:
    if INTEL:
        w = 64                   # ignored: SDM
c = low(aCX - 1, ASIZE)          # RCX; ECX with a 67 prefix
aCX = c
if c != 0 and zf == 0:
    t = low(rip + signed(rel), w)
    if not canonical(t):
        fault(GP, 0)
    rip = t

Run on AMD Zen 5 (EPYC 9645): 16 cases. Its branches for Intel's processors were not run: no Intel processor ran these forms.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`LOOPNE rel8`
`rel8`	explicit	read
`rCX`	implicit	read, write
`rIP`	implicit	read, write
`RFLAGS`	implicit	read

Flags

T tested; blank: not affected. How to read.

ZF
All forms
T

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Found or not#

On Zen 5#