Instruction
LWPINS
Inserts a record with a value of the program's choosing into the Lightweight Profiling ring buffer; LWP.
An AMD extension: Intel processors do not have this instruction.
- Extensions
- Forms
- 2 (2 XOP)
- Data
- Intel XED v2026.08.23
Forms
Latency and throughput
| Model | r32/64, m32, imm32 | r32/64, r32, imm32 |
|---|---|---|
| Piledriver | 100 / 0.5EX0 EX1 | 100 / 0.5EX0 EX1 |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 15 & 1:
fault(UD) # CPUID: no LWP
if not xcr0 >> 62 & 1: # LWP's state not enabled by the
fault(UD) # OS
a = lwp_cbaddr
cf = 0
if a: # running: a record of event 255
opts = load(a, 32)
t = ptsc() if opts >> 30 & 1 else 0
r = 255 | (lwp_cfg >> 32 & 0xFF) << 8 # CoreId
r |= (imm & 0xFFFF) << 16 # imm's low 16 bits, src2 (Data1),
r |= src2 << 32 | this_rip << 64 # this instruction's address,
r |= src1 << 128 | t << 192 # src1 (Data2), the time stamp
size = load(a + 4, 32) & 0xFFFFFFF
size -= size % 32
h = lwp_head
store(load(a + 8, 64) + h, 256, r) # at BufferBase + head
nh = (h + 32) % size
if nh == load(a + 64, 32): # BufferTailOffset: full
missed = load(a + 24, 64)
store(a + 24, 64, missed + 1)
if opts >> 29 & 1: # continuous mode: on over the
lwp_head = nh # oldest record
else: # synchronized: the next record
cf = 1 # goes over this one
else:
lwp_head = nh
# with LWP off it only clears CF. Past the LWPCB's threshold, with
# its interrupts on, LWP interrupts the program, later. XED lists
# src1 as written: the APM has LWPINS only read itRun on AMD Zen 5 (EPYC 9645): 4 cases. Its cases ran where CPUID reported no LWP, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
LWPINS r32/64, r/m32, imm32 | ||
r32/64 | explicit | write |
r/m32 | explicit | read |
imm32 | explicit | read |
RFLAGS | implicit | write |
Flags
| CF |
|---|
| All forms |
| M |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
LWP | LWP | Bulldozer, Piledriver |
More LWP instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.38, July 2026)
- AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.45, July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.