x86-64.net

Instruction

LZCNT

Counts the leading zero bits of an operand; APX adds a form that leaves the flags unchanged.

Extensions
Forms
6 (2 Legacy, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of LZCNT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
LZCNT r16/32/64, m16/32/64 LZCNT_GPRv_MEMvF3 0F BD /rLZCNT
LZCNT r16/32/64, r16/32/64 LZCNT_GPRv_GPRvF3 0F BD /rLZCNT
LZCNT r16/32/64, r16/32/64 LZCNT_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F5 /rAPX_F + LZCNT
LZCNT r16/32/64, m16/32/64 LZCNT_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F5 /rAPX_F + LZCNT
LZCNT r16/32/64, r16/32/64 NF LZCNT_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F5 /r NF=1APX_F + APX_NCI_NDD_NF + LZCNT
LZCNT r16/32/64, m16/32/64 NF LZCNT_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F5 /r NF=1APX_F + APX_NCI_NDD_NF + LZCNT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
LZCNT

LZCNT
CPUID.80000001H:ECX[5] LZCNT

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2
APX_F_LZCNT

APX_F + LZCNT
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.80000001H:ECX[5] LZCNT

Nova Lake, Diamond Rapids
APX_F_LZCNT_N3

APX_F + APX_NCI_NDD_NF + LZCNT
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF
CPUID.80000001H:ECX[5] LZCNT

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.