MASKMOVQ instruction (SSE)

Forms

Every encoding of MASKMOVQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MASKMOVQ mm, mm` MASKMOVQ_MMXq_MMXq	`NP 0F F7 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A masked store: each byte moves where the sign bit of the byte in the same place of mm2 is 1; elsewhere memory is left as it was.

Example sign bits of mm2: 10110010.

Result bytes 7 to 0: a7, unchanged, a5, a4, unchanged, unchanged, a1, unchanged.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = aDI                          # DS:rDI, EDI with a 67 prefix
if not canonical(a):
    fault(GP, 0)                 # even with no byte selected
for i in range(8):               # checked whatever the mask: Zen
    if not writable(a + i):      # 5 faulted at an unmapped rDI
        fault(PF)                # with no byte selected
for i in range(8):
    if mm2.b[i] >> 7:            # the top bit of each byte selects it
        store(a + i, 8, mm1.b[i])
# a segment prefix (FS, GS) adds its base to the address
# x87: TOP = 0, all tags valid

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MASKMOVQ mm, mm`
`mm`	explicit	read
`mm`	explicit	read
`m64 at [rDI]`	implicit	write
`rDI`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: mmx-nofp2

Attributes

What else XED records about the forms. How to read.

All forms: non-temporal hint; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions