MAXPD instruction (SSE2)

MAXPD keeps the larger double of each of two pairs, by the rule that VMAXPD and MAXPS set out: the first operand comes back only when it is greater than the second, so a NaN in either, or two zeros of any sign, give the second operand as it is. VMAXPD’s page also shows that a quiet NaN alone raises IE, as Intel’s manual says and AMD’s leaves out. MINPD is the mirror image.

The legacy encoding writes its result over the first operand and leaves bits 128 and up of the register as they were (see SSE and AVX for what mixing that with VEX code costs), and its memory operand must be aligned to 16 bytes. Zen 5’s two recorded cases, with the same doubles in a register and in memory, show the rule on NaNs:

a signaling NaN first and a quiet NaN second gave the quiet NaN, unchanged;
a quiet NaN first and 1.0 second gave 1.0, the NaN lost;
IE was set in both, and bits 511:128 of the destination stayed as they were.

In baseline code

MAXPD is SSE2, so x86-64 code uses it without options. In our builds at -O2, with the default target and with -march=x86-64-v2:

a[i] = b[i] > c[i] ? b[i] : c[i] over pointers is MAXPD in Clang 23, two per iteration, each after MOVUPD loads, and one MAXSD per element in GCC 14; over global arrays of fixed size both compilers emit MAXPD with the second operand read from memory.
A ReLU, b[i] > 0.0 ? b[i] : 0.0, is MAXPD against a register zeroed by XORPD in Clang, so a NaN comes out as 0.
C’s fmax must return the number when only one argument is a NaN. GCC calls the library function per element. Clang takes MAXPD with the operands swapped, which handles a NaN in the second argument, then finds NaNs in the first with CMPUNORDPD and picks the second argument there: with ANDPD, ANDNPD and ORPD for the default target, and with one BLENDVPD for x86-64-v2, which has SSE4.1.

Forms

Every encoding of MAXPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MAXPD xmm, m128` MAXPD_XMMpd_MEMpd	`66 0F 5F /r`	SSE2
`MAXPD xmm, xmm` MAXPD_XMMpd_XMMpd	`66 0F 5F /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm1 and xmm2. Result doubles 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    xmm1.f64[i] = fmax(a, b)
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MAXPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MAXPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_pd` `__m128d _mm_max_pd(__m128d __a, __m128d __b)`	`MAXPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In baseline code#