MAXPS instruction (SSE)

MAXPS keeps the larger single of each of four pairs, but it is not the symmetric maximum of mathematics: the first operand comes back only when it is greater than the second, and the second operand otherwise. MINPS explains the rule at length, and MAXPD the double form: a NaN in either operand, or two zeros of any sign, both give the second operand as it is. Zen 5’s recorded cases show the rule’s edges:

in a case with DAZ set, masked, comparing +0 against -0, and -0 against +0, from two of its four pairs, both gave the second operand’s zero, sign and all, matching the rule for two zeros;
in a masked case with DAZ clear and FTZ set, a signaling NaN kept as the second operand, by that same rule, came back unchanged rather than quieted, and set only IE, together with DE from the denormals in two other pairs of the same case.

With IM clear, so IE unmasked, a signaling NaN instead makes MAXPS fault with #XM: two such recorded cases, one with every exception unmasked, left the whole destination register exactly as it was, IE set but no element written, even for the lanes whose result would have been well defined.

In compiled code

GCC 14 and Clang 23 at -O2 compile a[i] = b[i] > c[i] ? b[i] : c[i] over pointers to a scalar MAXSS per element in GCC and to MAXPS, four at a time, in Clang. A ReLU, b[i] > 0.0f ? b[i] : 0.0f, is MAXSS against a zeroed register in Clang at either target; GCC compiles it to CMPLTSS and ANDPS at the default target but switches to MAXSS itself at -march=x86-64-v2, in both cases turning a NaN into 0. C’s fmaxf, which must return the number when only one argument is a NaN, stays a library call per element in GCC.

AMD’s latency spreadsheet for Zen 5 gives MAXPS one macro-op with a latency of two cycles, on pipes FP2 and FP3. The legacy encoding writes its result over the first operand and leaves bits 128 and up of the register as they were (see mixing SSE and AVX), and its memory operand must be aligned to 16 bytes. VMAXPS is the VEX and EVEX form, MAXSS the scalar one and MINPS the minimum.

Forms

Every encoding of MAXPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MAXPS xmm, m128` MAXPS_XMMps_MEMps	`NP 0F 5F /r`	SSE
`MAXPS xmm, xmm` MAXPS_XMMps_XMMps	`NP 0F 5F /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm1 and xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    xmm1.f32[i] = fmax(a, b)
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MAXPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MAXPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_ps` `__m128 _mm_max_ps(__m128 __a, __m128 __b)`	`MAXPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

In compiled code#