MAXSD instruction (SSE2)

MAXSD keeps the larger of the low doubles of its two operands and leaves the high double of the destination alone. It follows the rule of MAXPS, which MINPS explains at length: the first operand is returned only when it is greater than the second, so a NaN in either, or two zeros of any sign, give the second operand as it is. MAXPD covers the packed double form’s compiler idioms, the ternary, fmax and an array maximum among them, which carry over to this scalar form one instruction at a time. In the two cases recorded on Zen 5:

in a masked case, a quiet NaN against 1.0 read from memory gave 1.0, with IE set and the destination’s unrelated high double, also 1.0, left as it was;
in a masked, clean case, -1.0 against +infinity gave +infinity, with no flag set and the destination’s high double, a quiet NaN, untouched since only the low element takes part.

In compiled code

GCC 14 and Clang 23 at -O2 compile both a > b ? a : b and b < a ? a : b over double to a single MAXSD, as MAXPD’s page shows for the packed form. C’s fmax, which must return the number when only one argument is a NaN, is a library call in GCC; Clang inlines MAXSD with the operands swapped and a CMPUNORDSD fix-up, through ANDPD, ANDNPD and ORPD at the default target or one BLENDVPD at -march=x86-64-v2. An array maximum stays a chain of MAXSD in GCC even under -ffast-math; Clang then widens it to MAXPD two doubles at a time, the way MINPD’s page shows for the minimum.

The memory form reads eight bytes at any alignment, and the legacy form keeps bits 255:128 (see mixing SSE and AVX). AMD’s latency spreadsheet for Zen 5 gives MAXSD one macro-op with a latency of two cycles, on pipes FP2 and FP3. VMAXSD is the VEX and EVEX form, and MINSD the minimum.

Forms

Every encoding of MAXSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MAXSD xmm, m64` MAXSD_XMMsd_MEMsd	`F2 0F 5F /r`	SSE2
`MAXSD xmm, xmm` MAXSD_XMMsd_XMMsd	`F2 0F 5F /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = fmax(xmm1.f64[0], src2.f64[0])
# xmm1.q[1] keeps its value
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MAXSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MAXSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_sd` `__m128d _mm_max_sd(__m128d __a, __m128d __b)`	`MAXSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#