MAXSS instruction (SSE)

MAXSS keeps the larger of the low singles of its two operands and leaves singles 1 to 3 of the destination alone. It follows the rule of MAXPS, which MINPS explains at length: the first operand is returned only when it is greater than the second, so a NaN in either, or two zeros, give the second operand as it is. VMAXPS lists what Zen 5 recorded for NaNs and zeros. The two cases recorded for this form show that only the low element takes part:

the maximum of -0 and +0 was +0, the second operand, while singles 1 to 3 of both registers held NaNs, signaling ones among them, and IE stayed clear;
3.0 against 0.1 from memory kept 3.0, with 2.0, 0.5 and 1.0000001 above it unchanged.

The C idioms

a > b ? a : b over float is exactly the instruction’s rule, and so is b < a ? a : b: GCC 14 and Clang 23 at -O2 compile both to maxss xmm0, xmm1. The intrinsic _mm_max_ss gives the same. Beyond that, in our builds for the x86-64 baseline:

C’s fmaxf must return the number when one argument is a NaN. GCC calls the library; Clang inlines the instruction with the operands swapped, CMPUNORDSS of the first argument and a select by ANDPS, ANDNPS and ORPS.
A ReLU, x > 0.0f ? x : 0.0f, is MAXSS against a zeroed register in Clang and a CMPLTSS mask ANDed with x in GCC; both give 0 for a NaN.
The largest element of an array, m = a[i] > m ? a[i] : m, stays a chain of scalar maxima, one element at a time, in both. With -ffast-math, Clang turns it into MAXPS on two accumulators of four singles, while GCC keeps the scalar form, now with the element read from memory.

AMD’s latency spreadsheet for Zen 5 lists it at 2 cycles on pipes FP2 and FP3, like the packed form. The memory form reads four bytes at any alignment, and the legacy form keeps bits 255:128 (see mixing SSE and AVX). VMAXSS is the VEX and EVEX form, MAXSD the double one and MINSS the minimum.

Forms

Every encoding of MAXSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MAXSS xmm, m32` MAXSS_XMMss_MEMss	`F3 0F 5F /r`	SSE
`MAXSS xmm, xmm` MAXSS_XMMss_XMMss	`F3 0F 5F /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm1 and xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = fmax(xmm1.f32[0], src2.f32[0])
# xmm1.d[1] to [3] keep their values
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MAXSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MAXSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_ss` `__m128 _mm_max_ss(__m128 __a, __m128 __b)`	`MAXSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

The C idioms#