MCOMMIT instruction (MCOMMIT)

Forms

Every encoding of MCOMMIT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MCOMMIT` MCOMMIT	`F3 0F 01 FA`	MCOMMIT

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not efer >> 17 & 1:
    fault(UD)                    # the OS has not set EFER.MCOMMIT
cf = mcommit_ok()                # 1 when every store before it has
                                 # reached memory without an error
of = sf = zf = af = pf = 0       # at any CPL

Not run on a processor: no processor at hand reports MCOMMIT in CPUID.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MCOMMIT`
`RFLAGS`	implicit	write

Flags

M modified; blank: not affected. How to read.

CF
All forms
M

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`MCOMMIT` MCOMMIT	MCOMMIT `CPUID.80000008H:EBX[8]` MCOMMIT	Zen 2, Zen 3 Note: Only the EPYC 7002 (Zen 2) and EPYC 7003 (Zen 3) server processors have MCOMMIT. AMD's references for the Ryzen processors of Zen 2 and Zen 3 leave CPUID_Fn80000008_EBX[MCOMMIT] (bit 8) clear, and so do its references for Zen 4 and Zen 5, EPYC included.