MINPD instruction (SSE2)

MINPD keeps the smaller double of each of two pairs. The first operand comes back only when it is less than the second, and the second otherwise, so a NaN in either and two zeros of any sign give the second operand; MINPS explains the rule and how it matches C’s a < b ? a : b, and VMINPD has the VEX and EVEX forms. MAXPD is the mirror image.

What the legacy encoding adds is the usual for SSE: the result replaces the first operand, bits 128 and up of the register are kept (see SSE and AVX), and a memory operand must be aligned to 16 bytes. Zen 5’s recorded minpd xmm7, xmmword ptr [mem] shows the second operand winning:

min(-0, +0) gave +0, the second zero;
with a quiet NaN first and a signaling NaN second, the signaling NaN came back unchanged, not quieted, and IE was set.

The register case, minpd xmm4, xmm4 with -infinity and +infinity, left both as they were and set no flag: infinities are ordinary values here.

Minimum of an array

A loop such as m = b[i] < m ? b[i] : m depends on the order of the operands for NaNs and zeros, so a compiler may only spread it over the two halves of a register when told that neither matters. In our builds at -O2 for the default target, GCC 14 and Clang 23 keep a chain of MINSD without options, and GCC still does with -ffast-math. Clang then broadcasts the initial value with UNPCKLPD of the register with itself, takes the minimum of four doubles per iteration in two MINPD accumulators, combines them with a third, and finishes with UNPCKHPD and one MINSD on the last two elements.

C’s fmin returns the number when only one argument is a NaN: as for fmax on the MAXPD page, GCC calls the library function, and Clang follows each MINPD with CMPUNORDPD and a blend.

Forms

Every encoding of MINPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MINPD xmm, m128` MINPD_XMMpd_MEMpd	`66 0F 5D /r`	SSE2
`MINPD xmm, xmm` MINPD_XMMpd_XMMpd	`66 0F 5D /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm1 and xmm2. Result doubles 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    xmm1.f64[i] = fmin(a, b)
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MINPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MINPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_pd` `__m128d _mm_min_pd(__m128d __a, __m128d __b)`	`MINPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Minimum of an array#