MINPS instruction (SSE)

MINPS keeps the smaller single of each pair, but it is not the symmetric minimum of mathematics. It returns the first operand only when that is less than the second, and the second operand otherwise. So when either is a NaN, or both are zeros of any sign, the result is the second operand, whatever it holds: a NaN in the second operand is returned as it is, while a NaN in the first is lost. Intel’s and AMD’s manuals agree on this. MAXPS is the mirror image.

C’s conditional expression

The rule is exactly that of a < b ? a : b, which gives b whenever the comparison is false, and compilers use MINPS for it. GCC 14 and Clang 23 at -O2 compile it, for floats a and b in XMM0 and XMM1, to minss xmm0, xmm1, and a loop of such expressions to MINPS. Written the other way round, as C++’s std::min(a, b) is (b < a ? b : a), the operands swap: minss xmm1, xmm0, and a MOVAPS to return the result. A ReLU, x > 0 ? x : 0, becomes MAXPS with zero as the second operand, which also turns a NaN into 0.

fminf

C’s fminf returns the number when only one operand is a NaN, whichever of the two it is, so MINPS alone does not do. GCC 14 calls the library function. Clang 23 inlines MINSS with the operands swapped, which takes care of a NaN in the second argument, and adds a CMPUNORDSS test of the first and a blend (ANDPS, ANDNPS, ORPS) that picks the second argument where the first is a NaN. With -ffast-math, which lets the compiler assume there are no NaNs and ignore the sign of zero, both use MINSS and MINPS directly.

The zero rule matters too: MINPS(-0, +0) gives +0. Code that needs the minimum of IEEE 754-2019, in which -0 is less than +0 and a NaN input gives a NaN, can use VMINMAXPS on processors with AVX10.2; VMINPS is the VEX and EVEX form of MINPS, with the same rule.

Forms

Every encoding of MINPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MINPS xmm, m128` MINPS_XMMps_MEMps	`NP 0F 5D /r`	SSE
`MINPS xmm, xmm` MINPS_XMMps_XMMps	`NP 0F 5D /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm1 and xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    xmm1.f32[i] = fmin(a, b)
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MINPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MINPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_ps` `__m128 _mm_min_ps(__m128 __a, __m128 __b)`	`MINPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

C’s conditional expression#

fminf#