MINSD instruction (SSE2)

MINSD keeps the smaller of the low doubles of its operands and leaves the high double of the destination as it was. Its rule is that of MINPS, whose page explains it with C’s conditional expression and fminf: the first operand comes back only when it is less than the second, so a NaN in either, or two zeros, give the second operand. MINPD is the packed double form and MAXSS shows the scalar idioms for the maximum. In the two cases recorded on Zen 5:

1.0 against 0.0 gave 0.0; the destination’s high double, -1.0, stayed, and the -0.0 in the source’s high double played no part;
+infinity against +infinity read from memory gave +infinity, with no flag set.

Operand order in compiled code

GCC 14 and Clang 23 at -O2 compile a < b ? a : b over double to minsd xmm0, xmm1, and with b in memory to minsd xmm0, qword ptr [rdi]: unlike the square roots, the minimum reads its destination anyway, so the memory form costs no extra dependency. C++’s std::min(a, b) is b < a ? b : a, which returns a when the two compare equal or unordered; both compilers keep that meaning by swapping the operands, minsd xmm1, xmm0, and copying the result back with MOVAPD. A NaN in a therefore comes out of std::min(a, b) but not of a < b ? a : b.

C’s fmin returns the number when one argument is a NaN: GCC calls the library, while Clang inlines MINSD with the operands swapped and replaces the result with the second argument where CMPUNORDSD finds a NaN in the first, through ANDPD, ANDNPD and ORPD. The minimum of an array stays a chain of scalar minimums at -O2 in both compilers.

AMD’s latency spreadsheet for Zen 5 lists MINSD at 2 cycles on pipes FP2 and FP3. The memory form reads eight bytes at any alignment, and the legacy form keeps bits 255:128 (see mixing SSE and AVX). VMINSD is the VEX and EVEX form.

Forms

Every encoding of MINSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MINSD xmm, m64` MINSD_XMMsd_MEMsd	`F2 0F 5D /r`	SSE2
`MINSD xmm, xmm` MINSD_XMMsd_XMMsd	`F2 0F 5D /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = fmin(xmm1.f64[0], src2.f64[0])
# xmm1.q[1] keeps its value
# a NaN or two zeros: b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MINSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MINSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_sd` `__m128d _mm_min_sd(__m128d __a, __m128d __b)`	`MINSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Operand order in compiled code#