MONITOR

MONITOR is the first half of a wait. It arms the processor’s address monitor on the range that holds the address in RAX (DS by default, a segment override allowed), and a later MWAIT lets the core rest until something writes to that range. It reads no data and writes no register, but the address is checked as for a one-byte load: an unmapped page raises #PF, and Intel’s manual adds that it sets the page’s accessed bit. ECX must be 0, since no extension is defined, or it raises #GP; EDX carries hints that no processor defines.

Sizing the watched range#

The monitored range is not defined as a cache line: CPUID leaf 05H reports the smallest and the largest monitor-line size. Intel’s manual asks for the watched flag to fit in the smallest, so that a store to it always wakes the waiter, and for it to be padded to the largest, so that stores to unrelated neighbours do not wake it for nothing (volume 3, Section 11.10.5). Both manuals promise the monitor only on write-back memory.

Arm, check, then wait#

MWAIT does not re-arm the monitor, and events other than the awaited store end a wait. So the pair runs in a loop, and the flag is read again between MONITOR and MWAIT: a store that lands after the first check but before the monitor is armed would otherwise go unseen, and the core would sleep with its work already posted. Both manuals give this shape.

Who may run it#

Intel’s MONITOR runs only at CPL 0 and raises #UD elsewhere. AMD’s also runs at CPL 3 when the operating system sets MonMwaitUserEn in MSR C001_0015h, and AMD’s manual tells user code to test for #UD, not only CPUID leaf 1, ECX bit 3. Each vendor has a pair for user code instead: UMONITOR and UMWAIT on Intel’s processors, MONITORX and MWAITX on AMD’s.

The probe runs at CPL 3 in a Zen 5 guest whose CPUID reports no MONITOR, so this page has no recorded cases. AMD’s Zen 5 guide lists MONITOR as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(UD)                    # CPL 0 alone (AMD: unless the OS
                                 # sets HWCR's MonMwaitUserEn)
if rcx != 0:
    fault(GP, 0)                 # no extension is defined
a = low(rax, ASIZE)              # DS:rAX, EAX with a 67 prefix
if not canonical(a):
    fault(GP, 0)
if not readable(a):
    fault(PF)                    # the checks of a 1-byte read
# arms the monitor on the range that holds a, for MWAIT; EDX holds
# hints, which no processor defines

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MONITOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More MONITOR/MWAIT instructions

• MWAIT