Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MONITORX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MONITORX MONITORXNP 0F 01 FA
67 0F 01 FA
MONITORX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if ecx != 0:
    fault(GP, 0)                 # no extension is defined
a = low(rax, ASIZE)              # DS:rAX, EAX with a 67 prefix
if not canonical(a):
    fault(GP, 0)
if not readable(a):
    fault(PF)                    # the checks of a 1-byte read
# arms the monitor on the range that holds a, for MWAITX, at any
# privilege level; EDX holds hints, which no processor defines

Not run on a processor: the Zen 5 guest that ran the probe does not report MONITORX in CPUID.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
MONITORX
rAXimplicitread
ECXimplicitread
EDXimplicitread

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MONITORX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_monitorx void _mm_monitorx(void *__p, unsigned int __extensions, unsigned int __hints)

MONITORX Legacy -mmwaitx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
MONITORX

MONITORX
CPUID.80000001H:ECX[29] MONITORX

Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Note: XED gives MONITORX and MWAITX to its Zen 2 chip alone; GCC's -march=bdver4 (Excavator) and -march=znver1 and later enable them.

More MONITORX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.