Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MONTMUL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
REP MONTMUL REP_MONTMUL67 F3 0F A6 C0VIA_PADLOCK_PMM + VIA_PADLOCK_PMM_EN

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

via = cpuid_leaf(0xC0000001, 0)[3]
if via >> 12 & 3 != 3:
    fault(UD)                    # CPUID: no PMM, or it is off
if not cr4 >> 9 & 1:
    fault(UD)                    # no SSE
x = aSI                          # the context, any alignment:
z = load(x, 32)                  # m' = -1 / M modulo 2^32,
pa = load(x + 4, 32)             # then where A, B, T and M are,
pb = load(x + 8, 32)             # 16-byte aligned (and a scratch
pt = load(x + 12, 32)            # buffer at x + 20)
pm = load(x + 16, 32)
n = ecx                          # the numbers' length in bits
if 256 <= n <= 32768 and n % 128 == 0:
    a = load(pa, n)
    b = load(pb, n)
    m = load(pm, n)
    s = 0                        # A's words in turn, the lowest
    for i in range(n // 32):     # first: s stays below 2M
        s += (a >> 32 * i & 0xFFFFFFFF) * b
        q = s * z & 0xFFFFFFFF   # s + q * M: a multiple of 2^32
        s = s + q * m >> 32
    store(pt, n + 128, s)        # A * B / 2^n modulo M, or that
    ecx = 0                      # plus M: software subtracts M;
    edx = 0                      # T has 128 bits more for it
else:                            # a length the guide does not
    ecx = edx = UNDEFINED        # allow
eax = UNDEFINED                  # the multiplier's progress
# EAX must be 0 at the start, and T all zeros: the multiplier keeps
# its partial product there, so that an interrupt resumes it.
# Pointers and lengths are 32 bits, whatever the prefixes; in
# 64-bit mode XED decodes the form only with a 67 prefix

Run on AMD Zen 5 (EPYC 9645): 1 case. It ran where CPUID reported no PadLock PMM, and raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
REP MONTMUL
EAXimplicitread, write
ECXimplicitread, write
EDXimplicitwrite
m192 at ES:[rSI]implicitread, write
rSIimplicitread

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms
repeated: count in rCX

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
VIA_PADLOCK_MONTMUL

VIA_PADLOCK_PMM + VIA_PADLOCK_PMM_EN
CPUID.C0000001H:EDX[12] VIA_PADLOCK_PMM
CPUID.C0000001H:EDX[13] VIA_PADLOCK_PMM_EN

None in XED’s model.

More VIA PadLock instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Linux 7.3: drivers/crypto/padlock-aes.c and padlock-sha.c (VIA PadLock AES and SHA)
  3. Linux 7.3: drivers/char/hw_random/via-rng.c (VIA PadLock random number generator)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.