x86-64.net

Instruction

MOV

Copies data between registers, memory and immediates, and moves segment, control and debug registers; those last two only in ring 0.

Extensions
Forms
30 (30 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOV r8, imm8 MOV_GPR8_IMMb_C6r0C6 /0 ibBase instruction set
MOV m8, imm8 MOV_MEMb_IMMbC6 /0 ibBase instruction set
MOV r16/32/64, imm16/32 MOV_GPRv_IMMzC7 /0 iw/idBase instruction set
MOV m16/32/64, imm16/32 MOV_MEMv_IMMzC7 /0 iw/idBase instruction set
MOV r8, r8 MOV_GPR8_GPR8_8888 /rBase instruction set
MOV m8, r8 MOV_MEMb_GPR888 /rBase instruction set
MOV m16/32/64, r16/32/64 MOV_MEMv_GPRv89 /rBase instruction set
MOV r16/32/64, r16/32/64 MOV_GPRv_GPRv_8989 /rBase instruction set
MOV r8, m8 MOV_GPR8_MEMb8A /rBase instruction set
MOV r8, r8 MOV_GPR8_GPR8_8A8A /rBase instruction set
MOV r16/32/64, m16/32/64 MOV_GPRv_MEMv8B /rBase instruction set
MOV r16/32/64, r16/32/64 MOV_GPRv_GPRv_8B8B /rBase instruction set
MOV m16, sreg MOV_MEMw_SEG8C /rBase instruction set
MOV r16/32/64, sreg MOV_GPRv_SEG8C /rBase instruction set
MOV sreg, m16 MOV_SEG_MEMw8E /rBase instruction set
MOV sreg, r16 MOV_SEG_GPR168E /rBase instruction set
MOV AL, m8 MOV_AL_MEMbA0 moffsBase instruction set
MOV rAX, m16/32/64 MOV_OrAX_MEMvA1 moffsBase instruction set
MOV m8, AL MOV_MEMb_ALA2 moffsBase instruction set
MOV m16/32/64, rAX MOV_MEMv_OrAXA3 moffsBase instruction set
MOV r8, imm8 MOV_GPR8_IMMb_B0B0+r ibBase instruction set
MOV r16/32/64, imm16/32/64 MOV_GPRv_IMMvB8+r iw/id/ioBase instruction set
MOV cr, r32 not in 64-bit mode MOV_CR_CR_GPR320F 22 /rBase instruction set
MOV cr, r64 64-bit mode only MOV_CR_CR_GPR640F 22 /rBase instruction set
MOV r32, cr not in 64-bit mode MOV_CR_GPR32_CR0F 20 /rBase instruction set
MOV r64, cr 64-bit mode only MOV_CR_GPR64_CR0F 20 /rBase instruction set
MOV dr, r32 not in 64-bit mode MOV_DR_DR_GPR320F 23 /rBase instruction set
MOV dr, r64 64-bit mode only MOV_DR_DR_GPR640F 23 /rBase instruction set
MOV r32, dr not in 64-bit mode MOV_DR_GPR32_DR0F 21 /rBase instruction set
MOV r64, dr 64-bit mode only MOV_DR_GPR64_DR0F 21 /rBase instruction set

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOV, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_load_mask32 __mmask32 _load_mask32(__mmask32 *__A)

MOV r16/32/64, m16/32/64 Legacy -mavx512bw

_load_mask64 __mmask64 _load_mask64(__mmask64 *__A)

MOV r16/32/64, m16/32/64 Legacy -mavx512bw

_store_mask16 void _store_mask16(__mmask16 *__A, __mmask16 __B)

MOV m16/32/64, r16/32/64 Legacy -mavx512f

_store_mask32 void _store_mask32(__mmask32 *__A, __mmask32 __B)

MOV m16/32/64, r16/32/64 Legacy -mavx512bw

_store_mask64 void _store_mask64(__mmask64 *__A, __mmask64 __B)

MOV m16/32/64, r16/32/64 Legacy -mavx512bw

_store_mask8 void _store_mask8(__mmask8 *__A, __mmask8 __B)

MOV m8, r8 Legacy -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.