MOVAPD instruction (SSE2)

MOVAPD copies 16 bytes between XMM registers, or between an XMM register and memory aligned to 16 bytes, read as two doubles but not interpreted. It is MOVAPS with a 66 prefix, which came with SSE2: the same alignment fault, the same two register encodings (0F 28 and 0F 29 after the prefix, both run on Zen 5) and the same atomicity of aligned accesses that MOVDQA describes. AMD’s manual makes the fault independent of its misaligned SSE mode, as for MOVDQA. VMOVAPD is the VEX and EVEX form, which clears the register above the vector and masks by double. The legacy load leaves bits 128 and up as they were (see mixing SSE and AVX).

A byte for a name

The prefix buys nothing in the result, and Intel’s optimization manual recommends the PS form, a byte shorter, wherever the two do the same (Section 3.5.1.10). The same manual names MOVAPD in its rule against copying a register with MOVSD, which writes only the low double and so waits for the rest of the old value: copy all 128 bits instead (Section 3.5.2.6, Rule 39).

Compilers follow the data. In our builds at -O2, with the default target and with -march=x86-64-v2:

GCC 14 copies double values and __m128d vectors between registers with MOVAPD, as in double f(double a, double b) { return b; }, loads aligned arrays of doubles and _mm_load_pd with it, but stores them with MOVAPS.
Clang 23 uses MOVAPD for the loads and stores of a loop over aligned double arrays and for a copy after a double-precision instruction such as SUBSD, while a plain copy is MOVAPS and so are _mm_load_pd and _mm_store_pd.

AMD’s Zen 5 guide, asking for loads and stores of the full register width, names VMOVAPD as the choice over MOVAPD (Section 2.11.2). Zen 5’s four recorded cases cover both register encodings and the aligned load and store.

In the optimization guide

What the optimization guide says about MOVAPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Redwood Cove

Front end: Redwood Cove fuses a load into a register with the operation on that register that follows it.
Front end: Redwood Cove’s load-and-operate fusion takes only some loads, addresses and operations.

Forms

Every encoding of MOVAPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVAPD xmm, m128` MOVAPD_XMMpd_MEMpd	`66 0F 28 /r`	SSE2
`MOVAPD xmm, xmm` MOVAPD_XMMpd_XMMpd_0F28	`66 0F 28 /r`	SSE2
`MOVAPD m128, xmm` MOVAPD_MEMpd_XMMpd	`66 0F 29 /r`	SSE2
`MOVAPD xmm, xmm` MOVAPD_XMMpd_XMMpd_0F29	`66 0F 29 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each double is copied to the same place.

The store forms copy the same way, from the register to memory.

Result double i is double i of xmm2. Result doubles 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination: bits 128 and up are unchanged

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVAPD xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`MOVAPD xmm/m128, xmm`
`xmm/m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVAPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_load_pd` `__m128d _mm_load_pd(const double *__dp)`	`MOVAPD xmm, m128` Legacy -msse2
`_mm_store_pd` `void _mm_store_pd(double *__dp, __m128d __a)`	`MOVAPD m128, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

A byte for a name#