MOVAPS instruction (SSE)

MOVAPS copies 128 bits between XMM registers, or between an XMM register and memory aligned to 16 bytes; at a misaligned address it raises #GP, as MOVDQA does, whose page covers that rule and the atomicity of aligned moves. MOVUPS takes any address. The bits are not interpreted, so MOVAPS moves integers and doubles as well as singles.

The generic vector move

It is the shortest full-register copy: an opcode with no prefix, where MOVAPD and MOVDQA need 66. Intel’s optimization guide recommends the PS form over the PD one for that byte wherever the two do the same thing (Section 3.5.1.10). Clang 23 at -O2 copies a register with movaps xmm0, xmm1 when the copy is all there is, for float, double and integer vectors alike, but after an instruction on doubles or integers it uses the matching move: MOVAPD after SUBSD or SUBPD, MOVDQA after PSUBD. It also loads and stores aligned integer vectors with MOVAPS where no integer arithmetic follows. GCC 14 copies registers with MOVAPS, MOVAPD or MOVDQA by the type of the data, and stores all three kinds with MOVAPS. Both also fill aligned stack arrays with it, such as a 64-byte local buffer zeroed by four MOVAPS stores, relying on the stack alignment of the System V ABI.

Copying the whole register is what the guide asks for even when only the low element matters: MOVSS and MOVSD between registers write part of the destination and so depend on its old value, and Intel’s guide recommends MOVAPS, MOVAPD or MOVDQA instead (Section 3.5.2.4). Such copies are cheap. Intel’s guide lists MOVAPS between XMM or YMM registers among the moves that the Ivy Bridge microarchitecture executes in its front end, with no latency (Section 3.5.1.12), and AMD’s guide says that moves between XMM, YMM or ZMM registers have no latency on Zen 5 (Section 2.11.2).

Two encodings of one move

The page lists two register forms because there are two opcodes: 0F 28 writes the register in ModRM.reg, 0F 29 the one in ModRM.rm, so movaps xmm0, xmm1 can be encoded either way, with the same effect. GNU as picks 0F 28 unless the instruction carries the {store} prefix. VMOVAPS is the VEX and EVEX form, which needs 32-byte alignment for 256 bits and 64-byte alignment for 512.

In the optimization guide

What the optimization guide says about MOVAPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Move elimination: A register-to-register copy can be made at renaming, by pointing the destination at the physical register of the source; the move then has no latency and uses no execution unit.

Redwood Cove

Front end: Redwood Cove fuses a load into a register with the operation on that register that follows it.
Front end: Redwood Cove’s load-and-operate fusion takes only some loads, addresses and operations.

Silvermont to Goldmont Plus

Out-of-order and in-order execution: On Silvermont, put the stores of an unrolled multiply-add loop at its end, so that they do not block the next multiply.
Out-of-order and in-order execution: Goldmont eliminates register-to-register moves of XMM registers; Silvermont does not. sources differ

Forms

Every encoding of MOVAPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVAPS xmm, m128` MOVAPS_XMMps_MEMps	`NP 0F 28 /r`	SSE
`MOVAPS xmm, xmm` MOVAPS_XMMps_XMMps_0F28	`NP 0F 28 /r`	SSE
`MOVAPS m128, xmm` MOVAPS_MEMps_XMMps	`NP 0F 29 /r`	SSE
`MOVAPS xmm, xmm` MOVAPS_XMMps_XMMps_0F29	`NP 0F 29 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each single is copied to the same place.

The store forms copy the same way, from the register to memory.

Result single i is single i of xmm2. Result singles 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination: bits 128 and up are unchanged

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVAPS xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`MOVAPS xmm/m128, xmm`
`xmm/m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVAPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_load_ps` `__m128 _mm_load_ps(const float *__p)`	`MOVAPS xmm, m128` Legacy -msse
`_mm_store_ps` `void _mm_store_ps(float *__p, __m128 __a)`	`MOVAPS m128, xmm` Legacy -msse
`_mm_store_si128` `void _mm_store_si128(__m128i *__p, __m128i __b)`	`MOVAPS m128, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

The generic vector move#

Two encodings of one move#