x86-64.net

Instruction

MOVBE

Loads or stores a 16-, 32- or 64-bit value with its byte order reversed; APX adds a register-to-register form.

Extensions
Forms
5 (2 Legacy, 3 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVBE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVBE r16/32/64, m16/32/64 MOVBE_GPRv_MEMv0F 38 F0 /rMOVBE
MOVBE m16/32/64, r16/32/64 MOVBE_MEMv_GPRv0F 38 F1 /rMOVBE
MOVBE r16/32/64, r16/32/64 MOVBE_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 60 /r
EVEX.LLZ.NP.MAP4.SCALABLE 61 /r		APX_F + MOVBE
MOVBE r16/32/64, m16/32/64 MOVBE_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 60 /rAPX_F + MOVBE
MOVBE m16/32/64, r16/32/64 MOVBE_MEMv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 61 /rAPX_F + MOVBE

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVBE, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_loadbe_i16 short _loadbe_i16(const void *__P)

MOVBE r16/32/64, m16/32/64 Legacy -mmovbe

_loadbe_i32 int _loadbe_i32(const void *__P)

MOVBE r16/32/64, m16/32/64 Legacy -mmovbe

_loadbe_i64 long long _loadbe_i64(const void *__P)

MOVBE r16/32/64, m16/32/64 Legacy -mmovbe

_storebe_i16 void _storebe_i16(void *__P, short __D)

MOVBE m16/32/64, r16/32/64 Legacy -mmovbe

_storebe_i32 void _storebe_i32(void *__P, int __D)

MOVBE m16/32/64, r16/32/64 Legacy -mmovbe

_storebe_i64 void _storebe_i64(void *__P, long long __D)

MOVBE m16/32/64, r16/32/64 Legacy -mmovbe

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MOVBE

MOVBE
CPUID.01H:ECX[22] MOVBE

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
APX_F_MOVBE

APX_F + MOVBE
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.01H:ECX[22] MOVBE

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.