Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

MOVDDUP copies one double into both halves of an XMM register: the low double of a register, or eight bytes of memory. It is SSE3’s broadcast of a double and the double-precision side of MOVSLDUP, which repeats the even singles; VMOVDDUP does the same in each 128-bit lane of a wider register, and VBROADCASTSD fills a whole YMM or ZMM register.

The memory form reads only eight bytes, and they need not be aligned, unlike most legacy SSE memory operands; the result, like every legacy SSE result, keeps bits 128 and up of the register (see SSE and AVX). Zen 5’s recorded load and register cases both put the low double in both halves and left the upper bits as they were. No floating-point operation happens, so a NaN or a denormal is copied as it is.

SSE3 and the baseline

SSE3 is not part of the first x86-64 level, so code built for the default target does without MOVDDUP: GCC 14 broadcasts a double with unpcklpd xmm0, xmm0 (UNPCKLPD) and Clang 23 with MOVLHPS, after a separate load when the value comes from memory. Both refuse _mm_movedup_pd and _mm_loaddup_pd without -msse3.

-march=x86-64-v2 includes SSE3. In our builds at -O2 with it, both compilers load and broadcast _mm_set1_pd(*p) and _mm_loaddup_pd(p) with one movddup xmm0, qword ptr [rdi], and Clang broadcasts a register with MOVDDUP as well, for example the scalar of a[i] = b[i] * s before its vector loop. GCC keeps unpcklpd xmm0, xmm0 for a register, even for _mm_movedup_pd; the result is the same.

Forms

Every encoding of MOVDDUP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVDDUP xmm, m64 MOVDDUP_XMMdq_MEMqF2 0F 12 /rSSE3
MOVDDUP xmm, xmm MOVDDUP_XMMdq_XMMqF2 0F 12 /rSSE3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Duplicate: the low double of each 128-bit lane goes to both doubles of the lane.
MOVDDUPResult doubles 1 to 0: a0, a0.01xmm2or m64aa0a0xmm1

Result doubles 1 to 0: a0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    j = 0
    xmm1.q[i] = src2.q[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
MOVDDUP xmm, xmm/m64
xmmexplicitwrite
xmm/m64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVDDUP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_loaddup_pd __m128d _mm_loaddup_pd(const double *dp)

MOVDDUP xmm, m64 Legacy -msse3

_mm_movedup_pd __m128d _mm_movedup_pd(__m128d __a)

MOVDDUP xmm, xmm Legacy -msse3

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE3

SSE3
CPUID.01H:ECX[0] SSE3

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE3 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-47 (MOVDDUP)
  5. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.