MOVDIR64B

MOVDIR64B copies 64 bytes from memory to memory. It reads the source, an ordinary memory operand of any alignment, perhaps in several pieces, and writes the destination, whose address is in a general-purpose register (an offset in ES), with one 64-byte write that is never split. The destination must be aligned to 64 bytes, or it raises #GP. Intel’s optimization manual (Section 3.12.1) notes that no other instruction guarantees an atomic write wider than 8 bytes.

A doorbell for devices#

The write is a direct store, as MOVDIRI’s is: it follows the write-combining protocol whatever the destination’s memory type, uncacheable included, bypasses the caches and is never combined with later stores to the same address. That suits a device that takes a whole work descriptor through one memory-mapped register. Direct stores are weakly ordered, so a descriptor could reach the device before earlier writes it depends on; Intel’s manual recommends an SFENCE right before the direct store, and with _mm_sfence(); _movdir64b(portal, desc); GCC 14 and Clang 23 at -O2 (with -mmovdir64b) emit just that: SFENCE, then movdir64b rdi, zmmword ptr [rsi]. The manual adds that the descriptor itself, stored just before, needs no fence, since MOVDIR64B reads it from the same addresses, and that on Sapphire Rapids it is best aligned and written with 64-byte AVX-512 stores, so that the read can be forwarded from them.

ENQCMD shares the opcode bytes, 0F 38 F8, with an F2 prefix instead of 66. It writes 64 bytes the same way but replaces the first four with the thread’s PASID and a privilege bit, and reports in ZF whether the device accepted the command.

Address size, on Zen 5#

The register is 64 bits wide in 64-bit mode, 32 with a 67H prefix. On Zen 5 with the prefix, RCX = 53184B0610000000H wrote to 10000000H, the upper half ignored, and a source of EBX + 20000000H with EBX = F0000040H wrapped to 10000040H. Destinations 8 and 32 bytes past a 64-byte boundary raised #GP and left memory alone.

Of AMD’s processors, the page lists Zen 5 and Zen 6 as having MOVDIR64B (CPUID leaf 7, ECX bit 28), and GCC 14 enables it for -march=znver5 but not znver4. AMD’s Zen 5 guide lists it, with MOVDIRI, as microcoded. APX adds an EVEX form; Zen 5 has no APX, so it was not run.

In the optimization guide

What the optimization guide says about MOVDIR64B, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Loads, stores and caches: Sapphire Rapids added MOVDIRI and MOVDIR64B, weakly ordered stores for ringing a device’s doorbell without stalling the stores behind them.

Tremont

• Instruction set and Lakefield: Tremont adds UMWAIT, TPAUSE, CLWB, CLDEMOTE and the direct stores, which GCC enables for it. sources differ

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = low(dest, ASIZE)             # the register holds the address: 64 bits
                                 # wide, 32 with 67h; ES, no override
if a % 64 != 0:
    fault(GP, 0)                 # it must be 64-byte aligned
v = src.read()                   # 64 bytes, maybe in several reads
store(a, 512, v)                 # one 64-byte direct store: around the
                                 # caches, weakly ordered, never split

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

All forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVDIR64B, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More APX instructions

• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL

All 88 APX instructions