x86-64.net

Instruction

MOVDIR64B

Copies 64 bytes from memory to a 64-byte-aligned destination as one direct store that is written atomically and bypasses the caches.

Extensions
Forms
2 (1 Legacy, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVDIR64B that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVDIR64B r16, m512 MOVDIR64B_GPRa_MEM66 0F 38 F8 /rMOVDIR64B
MOVDIR64B r16/32/64, m512 MOVDIR64B_GPRav_MEMu32_APXEVEX.LLZ.66.MAP4.SCALABLE F8 /rAPX_F + MOVDIR64B

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVDIR64B, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_movdir64b void _movdir64b(void *__dst, const void *__src)

MOVDIR64B r16, m512 Legacy -mmovdir64b

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MOVDIR64B

MOVDIR64B
CPUID.(EAX=07H,ECX=0):ECX[28] MOVDIR64B

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Snow Ridge, Sierra Forest, Clearwater Forest
APX_F_MOVDIR64B

APX_F + MOVDIR64B
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):ECX[28] MOVDIR64B

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.