x86-64.net

Instruction

MOVDIRI

Stores a 32- or 64-bit register to memory as a direct store that bypasses the caches.

Extensions
Forms
3 (2 Legacy, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVDIRI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVDIRI m32, r32 MOVDIRI_MEMu32_GPR32u32NP 0F 38 F9 /rMOVDIRI
MOVDIRI m64, r64 64-bit mode only MOVDIRI_MEMu64_GPR64u64REX.W 0F 38 F9 /rMOVDIRI
MOVDIRI m32/64, r32/64 MOVDIRI_MEMyu_GPRyu_APXEVEX.LLZ.NP.MAP4.SCALABLE F9 /rAPX_F + MOVDIRI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVDIRI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_directstoreu_u32 void _directstoreu_u32(void *__dst, unsigned int __value)

MOVDIRI m32, r32 Legacy -mmovdiri

_directstoreu_u64 void _directstoreu_u64(void *__dst, unsigned long __value)

MOVDIRI m64, r64 Legacy -mmovdiri

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MOVDIRI

MOVDIRI
CPUID.(EAX=07H,ECX=0):ECX[27] MOVDIRI

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Snow Ridge, Sierra Forest, Clearwater Forest
APX_F_MOVDIRI

APX_F + MOVDIRI
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):ECX[27] MOVDIRI

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.