MOVDIRI

MOVDIRI stores a general-purpose register of 32 or 64 bits to memory as a direct store: it writes around the caches with the write-combining protocol, whatever the memory type of the destination, and never merges with a later store to the same address. If the line is in a cache it is first written back, when modified, and invalidated. The destination must be memory; there is no register form and no 8- or 16-bit form. MOVDIR64B, whose page covers the shared semantics in more detail, does the same for a whole 64-byte line.

Small doorbells#

A device that takes work from a ring of descriptors is told about new ones by a write of the ring’s tail to one of its registers, usually mapped uncacheable. Ordinary stores to such memory are strongly ordered, so later stores wait behind the slow write to the device; Intel’s optimization manual describes how that holds back the store buffer and why direct stores, being weakly ordered, avoid it (Section 3.12.1). The same weak ordering means the doorbell could overtake the descriptors written before it, so the manual has software put an SFENCE first. With -mmovdiri, GCC 14 and Clang 23 at -O2 compile _mm_sfence(); _directstoreu_u64(reg, v); to sfence and movdiri qword ptr [rdi], rsi.

Alignment#

A destination aligned to its size arrives at the device in one undivided write; Intel’s manual guarantees nothing more for a misaligned one, which is split in two parts that may arrive in either order. No exception reports the misalignment, except #AC where alignment checking is on. Zen 5’s recorded cases, eight-byte stores to an address four bytes past alignment among them, wrote the value like an ordinary MOV, which is all a single thread can see.

Which processors#

Intel’s manuals differ on its age: the optimization manual says Sapphire Rapids introduced the direct stores, while the SDM’s first volume names Tremont and Tiger Lake as having them too, and GCC 14 enables -mmovdiri for -march=tremont and -march=tigerlake. Of AMD’s processors the page lists Zen 5 and Zen 6, and GCC 14 enables it for znver5 but not znver4; AMD’s Zen 5 guide lists it as microcoded. APX adds an EVEX form for its new registers.

In the optimization guide

What the optimization guide says about MOVDIRI, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Loads, stores and caches: Sapphire Rapids added MOVDIRI and MOVDIR64B, weakly ordered stores for ringing a device’s doorbell without stalling the stores behind them.

Tremont

• Instruction set and Lakefield: Tremont adds UMWAIT, TPAUSE, CLWB, CLDEMOTE and the direct stores, which GCC enables for it. sources differ

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src)                  # a direct store: around the caches, weakly
                                 # ordered; one write when dest is aligned to
                                 # its size, else two, in either order

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVDIRI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More APX instructions

• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR

All 88 APX instructions