MOVDQA instruction (SSE2)

MOVDQA moves 16 bytes between XMM registers and memory, as MOVDQU does, but only at addresses that are multiples of 16. A misaligned memory operand raises #GP(0), in every processor mode and whether alignment checking is on or not; this is not an #AC. AMD’s manual adds that its misaligned SSE mode (MXCSR.MM), which lets other legacy SSE instructions take unaligned operands on processors that report it, does not relax MOVDQA.

The instruction suits memory whose alignment the program controls: stack slots, which the System V stack rule keeps aligned to 16 bytes at each call, arrays declared with alignas(16), and constants that the compiler places on 16-byte boundaries. A function entered with RSP off by 8, for example from hand-written assembly that breaks the rule, can therefore crash at an aligned move the compiler made for a local variable, far from the actual mistake.

On processors that report AVX, the access is also atomic: another processor sees all 16 bytes old or all new. Intel’s manual guarantees this for MOVDQA, MOVAPS and MOVAPD and their 128-bit VEX and unmasked EVEX forms; AMD’s for any aligned 16-byte load or store of cacheable memory, which includes MOVDQU at an aligned address.

MOVAPS makes the same move with the same alignment rule, in an encoding one byte shorter (no 66 prefix), and compilers use it for integer data too: at -O2, Clang 23 emits MOVAPS for both _mm_load_si128 and _mm_store_si128, and GCC 14 for the store.

The other encodings:

VEX (VMOVDQA): 128 and 256 bits, the 256-bit form aligned to 32 bytes. It is one of the few VEX instructions that keep an alignment rule. The 128-bit form clears bits 128 and up of the destination register, which the legacy form leaves unchanged.
EVEX (VMOVDQA32 and VMOVDQA64): masked moves of doublewords or quadwords, aligned to the full vector size (16, 32 or 64 bytes) even when the mask selects only some elements.

In the optimization guide

What the optimization guide says about MOVDQA, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Move elimination: A register-to-register copy can be made at renaming, by pointing the destination at the physical register of the source; the move then has no latency and uses no execution unit.

Jaguar and Puma

Integer execution: xor, sub and cmp of a register with itself, and pxor, pandn, psub*, pcmpeq*, pcmpgt*, xorps and xorpd likewise, do not wait for the old value, and sbb waits only for the carry; ANDNPS and ANDNPD join them on Jaguar.

Redwood Cove

Front end: Redwood Cove fuses a load into a register with the operation on that register that follows it.
Front end: Redwood Cove’s load-and-operate fusion takes only some loads, addresses and operations.

Silvermont to Goldmont Plus

Out-of-order and in-order execution: Goldmont eliminates register-to-register moves of XMM registers; Silvermont does not. sources differ

Forms

Every encoding of MOVDQA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVDQA m128, xmm` MOVDQA_MEMdq_XMMdq	`66 0F 7F /r`	SSE2
`MOVDQA xmm, xmm` MOVDQA_XMMdq_XMMdq_0F7F	`66 0F 7F /r`	SSE2
`MOVDQA xmm, m128` MOVDQA_XMMdq_MEMdq	`66 0F 6F /r`	SSE2
`MOVDQA xmm, xmm` MOVDQA_XMMdq_XMMdq_0F6F	`66 0F 6F /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each doubleword is copied to the same place.

The store forms copy the same way, from the register to memory.

Result doubleword i is doubleword i of xmm2. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination: bits 128 and up are unchanged

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVDQA xmm/m128, xmm`
`xmm/m128`	explicit	write
`xmm`	explicit	read
`MOVDQA xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions