MOVHLPS instruction (SSE)

MOVHLPS copies the high 64 bits of its second register to the low 64 bits of the first and keeps the first’s high half: movhlps xmm0, xmm1 leaves xmm1[127:64] in bits 63:0 of XMM0. It moves bits, two singles or one double, without looking at them. Its opcode, 0F 12, is that of MOVLPS: with a memory operand the byte pair loads the low half from memory, and with a register in the ModRM byte it is this instruction. MOVLHPS is the reverse move, with 0F 16 shared with MOVHPS, and VMOVHLPS the VEX and EVEX form, which takes the high half of one source and the high half of another and clears the rest of the register.

Being an SSE instruction from the start, it needs no option. Like other legacy SSE instructions it keeps bits 128 and up (see SSE and AVX). Zen 5’s recorded movhlps xmm7, xmm11 put the high quadword of XMM11 in the low quadword of XMM7 and left XMM7’s high quadword and upper bits as they were.

In horizontal sums

_mm_movehl_ps(a, b) gives b’s high pair below and a’s above, and its common use is folding a vector in half before adding. In our builds at -O2, GCC 14 compiles a sum of four floats written with _mm_add_ps(v, _mm_movehl_ps(v, v)) to a MOVAPS copy, MOVHLPS and ADDPS. Clang 23 replaces the MOVHLPS with UNPCKHPD, which moves the same 64 bits, and emits MOVHLPS for the intrinsic on its own. The copy is there because MOVHLPS overwrites its first operand while v is still needed for the add; VMOVHLPS, which names a separate destination, needs none.

Forms

Every encoding of MOVHLPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVHLPS xmm, xmm` MOVHLPS_XMMq_XMMq	`NP 0F 12 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The high quadword of xmm2 becomes the low quadword of the result; the high quadword comes from xmm1.

Result quadwords 1 to 0: a1, b1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.q[0] = xmm2.q[1]  # xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVHLPS xmm, xmm`
`xmm`	explicit	read, write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_7

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

In horizontal sums#