MOVHPD instruction (SSE2)

MOVHPD, from SSE2, moves one double between memory and the high half of an XMM register. The load replaces bits 127:64 and keeps bits 63:0; the store writes those eight bytes and nothing else. There is no register to register form: between registers, UNPCKLPD or MOVLHPS fill the high half, and UNPCKHPD or MOVHLPS bring it down. MOVHPS does exactly the same with no 66 prefix, and MOVLPD is the low-half twin. The memory operand is eight bytes with no alignment requirement, and the load, like other legacy SSE instructions, keeps bits 128 and up of the register (see SSE and AVX).

Zen 5’s recorded load, movhpd xmm4, qword ptr [mem], kept the low double of XMM4 and put the eight bytes above it; the store, movhpd qword ptr [mem], xmm4, wrote the high double of XMM4 and left the bytes after it as they were.

Building a vector from two places

The load merges, so the register’s old low half is an input: MOVHPD usually follows a MOVSD load, which clears the high half, to gather two doubles from different addresses. In our builds at -O2, GCC 14 compiles (__m128d){*p, *q} to that pair, and a loop that interleaves two arrays of doubles into one to a MOVSD, a MOVHPD and a MOVUPS store per pair. _mm_loadh_pd is one MOVHPD in GCC, and _mm_storeh_pd, or storing element 1 of a vector, is the store form. Clang 23 writes all of these with MOVHPS instead, a byte shorter, and interleaves the arrays with whole-vector loads, MOVLHPS and UNPCKHPD.

AMD’s Zen 5 guide recommends loading and storing a register whole rather than in halves with MOVLPD and MOVHPD, and placing the loads of two halves next to each other when they cannot be avoided (Section 2.11.2).

In the optimization guide

What the optimization guide says about MOVHPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Partial register and flag writes: Scalar SSE instructions that write only the low element of an XMM register keep the rest of it, and so wait for its last writer: movss and movsd between registers, movlpd and movhpd from memory, and conversions and square roots such as cvtsi2sd and sqrtss.

Forms

Every encoding of MOVHPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVHPD xmm, m64` MOVHPD_XMMsd_MEMq	`66 0F 16 /r`	SSE2
`MOVHPD m64, xmm` MOVHPD_MEMq_XMMsd	`66 0F 17 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the high half: m64 becomes the high quadword of the result; the other quadword comes from xmm1.MOVHPD xmm, m64

Result quadwords 1 to 0: b0, a0.

A store of the high half: quadword 1 of xmm2 goes to m64.MOVHPD m64, xmm

m64 receives quadword 1 of xmm2: a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

MOVHPD xmm, m64

xmm1.q[1] = mem.q[0]  # xmm1.q[0] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

MOVHPD m64, xmm

mem.q[0] = xmm2.q[1]

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVHPD xmm, m64`
`xmm`	explicit	read, write
`m64`	explicit	read
`MOVHPD m64, xmm`
`m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVHPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadh_pd` `__m128d _mm_loadh_pd(__m128d __a, const double *__dp)`	`MOVHPD xmm, m64` Legacy -msse2
`_mm_loadh_pi` `__m128 _mm_loadh_pi(__m128 __a, const __m64 *__p)`	`MOVHPD xmm, m64` Legacy -msse
`_mm_storeh_pd` `void _mm_storeh_pd(double *__dp, __m128d __a)`	`MOVHPD m64, xmm` Legacy -msse2
`_mm_storeh_pi` `void _mm_storeh_pi(__m64 *__p, __m128 __a)`	`MOVHPD m64, xmm` Legacy -msse Clang's comment names VPEXTRQ; this intrinsic stores the upper half of a vector to memory, and Clang emits MOVHPD or VMOVHPD.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Building a vector from two places#