MOVHPS instruction (SSE)

MOVHPS moves 64 bits, two singles, between memory and the high half of an XMM register: the load replaces bits 127:64 and keeps bits 63:0, the store writes those eight bytes and no others. It is the SSE original of MOVHPD, which does the same with a 66 prefix and whose page explains how the merging load builds a vector from two places. With a register in place of memory, its opcode 0F 16 is MOVLHPS. The memory operand need not be aligned, and the legacy load keeps bits 128 and up (see mixing SSE and AVX), while VMOVHPS takes the low half from a second register and zeros everything above bit 127. On Zen 5, the recorded movhps xmm0, qword ptr [mem] kept XMM0’s low quadword and its bits 511:128 and placed the eight bytes above, and the store movhps qword ptr [mem], xmm0 wrote XMM0’s high quadword and left the following bytes as they were.

Pairs of floats

In our builds at -O2 for the x86-64 baseline:

_mm_loadh_pi and _mm_storeh_pi, whose pointers have the MMX type __m64 *, are MOVHPS in GCC 14 and Clang 23.
Building (__m128){p[0], p[1], q[0], q[1]} from two pairs is a MOVSD and a MOVHPS in Clang; GCC loads four single floats with MOVSS and combines them with UNPCKLPS and MOVLHPS.
Storing elements 2 and 3 of a vector to p[0] and p[1] is the store form in Clang, and PSRLDQ by 8 and a MOVLPS store in GCC.
Splitting an array of float pairs into two arrays, Clang loads each output vector in halves, with MOVSD and MOVHPS; GCC loads whole vectors and rearranges them with MOVLHPS and SHUFPS.

Both vendors advise against such halves. Intel’s optimization manual prefers 16-byte loads followed by shuffles to loading halves with MOVLPS and MOVHPS, which adds a dependency (Section 7.5.1.2), and AMD’s Zen 5 guide recommends whole-register loads and stores, with any unavoidable half loads placed next to each other (Section 2.11.2). Its latency spreadsheet gives the load one macro-op and the store two.

Forms

Every encoding of MOVHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVHPS xmm, m64` MOVHPS_XMMq_MEMq	`NP 0F 16 /r`	SSE
`MOVHPS m64, xmm` MOVHPS_MEMq_XMMps	`NP 0F 17 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the high half: m64 becomes the high quadword of the result; the other quadword comes from xmm1.MOVHPS xmm, m64

Result quadwords 1 to 0: b0, a0.

A store of the high half: quadword 1 of xmm2 goes to m64.MOVHPS m64, xmm

m64 receives quadword 1 of xmm2: a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

MOVHPS xmm, m64

xmm1.q[1] = mem.q[0]  # xmm1.q[0] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

MOVHPS m64, xmm

mem.q[0] = xmm2.q[1]

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVHPS xmm, m64`
`xmm`	explicit	read, write
`m64`	explicit	read
`MOVHPS m64, xmm`
`m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Pairs of floats#