MOVLHPS instruction (SSE)

MOVLHPS copies the low 64 bits of its second register to the high 64 bits of the first and keeps the first’s low half: movlhps xmm0, xmm1 puts xmm1[63:0] in bits 127:64 of XMM0. It is the reverse of MOVHLPS, and like it a register-only form whose opcode, 0F 16, loads the high half from memory as MOVHPS when the ModRM byte names memory. VMOVLHPS is the VEX and EVEX form, with a separate destination. Nothing is interpreted, so the 64 bits may be two singles, one double or an integer; and as in every legacy SSE instruction, bits 128 and up of the register stay as they were (see SSE and AVX). Zen 5’s recorded movlhps xmm8, xmm15 kept the low quadword of XMM8 and placed the low quadword of XMM15 above it.

A shorter UNPCKLPD

With registers, MOVLHPS gives the same result as UNPCKLPD and needs no 66 prefix, so it is one byte shorter, and Clang 23 uses it for doubles too. In our builds at -O2 for the default target, Clang compiles _mm_set1_pd(x) to movlhps xmm0, xmm0, and _mm_set_pd(b, a) and storing x to element 1 of a __m128d to movlhps xmm0, xmm1, where GCC 14 emits UNPCKLPD for all three. Clang’s vectorized loops that split an array of complex doubles into real and imaginary parts take the real parts with MOVLHPS and the imaginary ones with UNPCKHPD.

GCC uses MOVLHPS where the source says so, for _mm_movelh_ps, also after two eight-byte loads with MOVQ that build a vector of four floats from two pairs; Clang loads the second pair straight into the high half with MOVHPS instead.

Forms

Every encoding of MOVLHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVLHPS xmm, xmm` MOVLHPS_XMMq_XMMq	`NP 0F 16 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low quadword of xmm2 becomes the high quadword of the result; the low quadword comes from xmm1.

Result quadwords 1 to 0: b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.q[1] = xmm2.q[0]  # xmm1.q[0] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVLHPS xmm, xmm`
`xmm`	explicit	read, write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_7

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

A shorter UNPCKLPD#