MOVLPD instruction (SSE2)

MOVLPD, from SSE2, moves one double between memory and the low half of an XMM register. The load replaces bits 63:0 and keeps bits 127:64, unlike a MOVSD load, which clears them; the store writes eight bytes, as a MOVSD store does. MOVHPD is the high-half twin and explains what the pair is for, and MOVLPS is the same instruction with no 66 prefix. There is no register to register form; MOVSD between registers is the merging move. The memory operand need not be aligned, and the load keeps bits 128 and up of the register (see SSE and AVX).

Zen 5’s recorded cases: movlpd xmm0, qword ptr [mem] replaced the low double of XMM0 and kept the high one, and movlpd qword ptr [mem], xmm7 wrote the low double of XMM7 and left the next bytes alone.

Where compilers use it

In our builds at -O2, GCC 14 compiles _mm_loadl_pd(a, p), or assigning *p to element 0 of a __m128d, to movlpd xmm0, QWORD PTR [rdi], and _mm_storel_pd to the store; Clang 23 uses MOVLPS for both. For a plain double, both compilers load with MOVSD, which does not depend on the register’s old contents. Clang also stored a single result with MOVLPD in the scalar tail of a vectorized loop, where MOVSD would have done the same.

The merging load has a cost and a remedy on Zen 5. AMD’s guide recommends whole-register loads over MOVLPD and MOVHPD halves (Section 2.11.2), and lists MOVLPD xmm, [mem] among the instructions whose merge can skip waiting for the register’s old value when the processor has tracked its upper bits as cleared to zero (Section 2.11.5).

In the optimization guide

What the optimization guide says about MOVLPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Partial register and flag writes: Scalar SSE instructions that write only the low element of an XMM register keep the rest of it, and so wait for its last writer: movss and movsd between registers, movlpd and movhpd from memory, and conversions and square roots such as cvtsi2sd and sqrtss.

Forms

Every encoding of MOVLPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVLPD xmm, m64` MOVLPD_XMMsd_MEMq	`66 0F 12 /r`	SSE2
`MOVLPD m64, xmm` MOVLPD_MEMq_XMMsd	`66 0F 13 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the low half: m64 becomes the low quadword of the result; the other quadword comes from xmm1.MOVLPD xmm, m64

Result quadwords 1 to 0: a1, b0.

A store of the low half: quadword 0 of xmm2 goes to m64.MOVLPD m64, xmm

m64 receives quadword 0 of xmm2: a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

MOVLPD xmm, m64

xmm1.q[0] = mem.q[0]  # xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

MOVLPD m64, xmm

mem.q[0] = xmm2.q[0]

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVLPD xmm, m64`
`xmm`	explicit	read, write
`m64`	explicit	read
`MOVLPD m64, xmm`
`m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVLPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadl_pd` `__m128d _mm_loadl_pd(__m128d __a, const double *__dp)`	`MOVLPD xmm, m64` Legacy -msse2
`_mm_loadl_pi` `__m128 _mm_loadl_pi(__m128 __a, const __m64 *__p)`	`MOVLPD xmm, m64` Legacy -msse
`_mm_storel_pd` `void _mm_storel_pd(double *__dp, __m128d __a)`	`MOVLPD m64, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Where compilers use it#