MOVLPS instruction (SSE)

MOVLPS moves 64 bits, two singles, between memory and the low half of an XMM register. The load replaces bits 63:0 and keeps bits 127:64, unlike a MOVSD or MOVQ load, which clears them; the store writes eight bytes. MOVLPD is the same move with a 66 prefix, and MOVHPS the high-half twin, whose page covers the pairs of floats that compilers move with both. With a register in place of memory, the opcode 0F 12 is MOVHLPS. The memory operand need not be aligned, and the legacy load keeps bits 128 and up (see mixing SSE and AVX), where VMOVLPS zeros them. Zen 5’s recorded movlps xmm1, qword ptr [mem] replaced the low quadword of XMM1 and kept its high quadword and bits 511:128, and movlps qword ptr [mem], xmm12 wrote XMM12’s low quadword and left the next bytes alone.

Where compilers use it

In our builds at -O2, GCC 14 and Clang 23 compile _mm_loadl_pi and _mm_storel_pi to MOVLPS, and storing elements 0 and 1 of a __m128 to two floats in memory to the store form; Clang also uses MOVLPS for _mm_loadl_pd, a byte shorter than MOVLPD. To load a pair of floats into an otherwise unused register, Clang prefers MOVSD, which does not depend on the register’s old contents.

The merging load is what both vendors’ guides discuss. Intel’s optimization manual prefers 16-byte loads and shuffles to loading halves with MOVLPS and MOVHPS (Section 7.5.1.2). AMD’s Zen 5 guide recommends whole-register loads too (Section 2.11.2), but lists MOVLPS xmm1,[mem] among the instructions whose merge can skip waiting for the register’s old value when the processor knows its upper bits to be zero (Section 2.11.5). Its latency spreadsheet gives MOVLPS one macro-op, two per cycle.

Forms

Every encoding of MOVLPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVLPS xmm, m64` MOVLPS_XMMq_MEMq	`NP 0F 12 /r`	SSE
`MOVLPS m64, xmm` MOVLPS_MEMq_XMMq	`NP 0F 13 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the low half: m64 becomes the low quadword of the result; the other quadword comes from xmm1.MOVLPS xmm, m64

Result quadwords 1 to 0: a1, b0.

A store of the low half: quadword 0 of xmm2 goes to m64.MOVLPS m64, xmm

m64 receives quadword 0 of xmm2: a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

MOVLPS xmm, m64

xmm1.q[0] = mem.q[0]  # xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

MOVLPS m64, xmm

mem.q[0] = xmm2.q[0]

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVLPS xmm, m64`
`xmm`	explicit	read, write
`m64`	explicit	read
`MOVLPS m64, xmm`
`m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Where compilers use it#