MOVMSKPS instruction (SSE)

MOVMSKPS copies the sign bits of the four doublewords of an XMM register into bits 3:0 of a general-purpose register and clears every bit above, the whole 64-bit register included. On Zen 5, movmskps ecx, xmm1 with -FLT_MAX, 1.0, -1.0 and 2.0 left RCX = 5. It is PMOVMSKB for four-byte elements, and that page’s uses carry over: a test against zero for “any”, against 0Fh for “all”, TZCNT for the first.

A sign bit is not a comparison

Applied to the result of CMPPS, MOVMSKPS says which elements passed. Applied to raw floats, it reads their sign bits, which are set for -0.0 and for NaNs with the sign bit set as well, so it gives C’s signbit, not x < 0. Testing for a NaN anywhere in a vector takes CMPUNORDPS of the vector with itself and then MOVMSKPS.

Integer data

The instruction does not care whether the data are floats. Clang 23 uses it for doubleword compares: for _mm_movemask_epi8(_mm_cmpeq_epi32(a, b)) != 0 it emits PCMPEQD and MOVMSKPS, where GCC 14 keeps the PMOVMSKB that the source asked for; both answer the same question, from 4 bits instead of 16. There is no doubleword form of PMOVMSKB, so _mm_movemask_ps(_mm_castsi128_ps(v)) is the usual way to collect the signs of four ints.

In compiled code

With GCC 14 and Clang 23 at -O2, _mm_movemask_ps(_mm_cmplt_ps(a, b)) becomes CMPLTPS and MOVMSKPS in both. They differ on “all”: GCC compares the mask with 15, Clang inverts the comparison (CMPNLTPS) and tests for zero. Written with GCC’s vector extensions as (m[0] | m[1] | m[2] | m[3]) != 0, the “any” test became MOVMSKPS in Clang, and two shifts, two ORs and a MOVD in GCC.

MOVMSKPD takes the two sign bits of doubles. VMOVMSKPS, the VEX form, gives 8 bits from a YMM register. AVX-512 has no EVEX form: its compares write mask registers directly, and VPMOVD2M collects the sign bits of doublewords into one. AMD’s Zen 5 guide lists MOVMSKPS as one macro-op.

Forms

Every encoding of MOVMSKPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVMSKPS r32, xmm` MOVMSKPS_GPR32_XMMps	`NP 0F 50 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each single of the source sets one bit of r32, bit i for single i; the bits above them are cleared.

Bit i of r32 comes from single i of xmm2. Result bits 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = 0
for i in range(4):
    r |= (xmm2.sd[i] < 0) << i
dest.write(r)  # the other bits are cleared

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVMSKPS r32, xmm`
`r32`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_7

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVMSKPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movemask_ps` `int _mm_movemask_ps(__m128 __a)`	`MOVMSKPS r32, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

A sign bit is not a comparison#

Integer data#

In compiled code#