MOVNTDQ instruction (SSE2)

MOVNTDQ stores the 16 bytes of an XMM register with a non-temporal hint: the data goes to a write-combining buffer and from there to memory, without reading the line into the caches first and without leaving it there. It is the 16-byte member of the family that MOVNTI describes, weakly ordered like it: a loop of MOVNTDQs needs an SFENCE before another thread or a device is told that the data is ready. The storing thread itself needs no fence to read them back (Intel’s optimization manual, Section 9.4.2.1).

Aligned, and best in whole lines

The address must be a multiple of 16, or MOVNTDQ raises #GP; there is no unaligned form. A copy or fill routine therefore stores the head and tail of a buffer with ordinary moves and streams the aligned middle. Both optimization guides tie the gain to whole lines: four MOVNTDQs in a row from a 64-byte boundary fill a line with one write to memory and no read for ownership (Intel’s, Section 9.4.1.2), while a partly written buffer may stay open for a long time (AMD’s for Zen 5, Section 2.13.4).

The memory type overrides the hint: to uncacheable or write-protected memory, MOVNTDQ is an ordinary store of that type. On write-back memory, a line already cached may be updated in place or evicted, depending on the processor (Section 9.4.1.3).

From C

_mm_stream_si128(p, v) needs only SSE2. GCC 14 at -O2 emits MOVNTDQ for it, Clang 23 MOVNTPS, which stores the same 16 bytes and is a byte shorter, having no 66 prefix; with -mavx2 they emit VMOVNTDQ and VMOVNTPS. Neither adds a fence, and a C11 release store of a flag after the loop compiles to a plain MOV, which does not order the streaming stores before it.

Zen 5 and the wider forms

AMD’s Zen 5 guide lists MOVNTDQ as one macro-op, two per cycle. It also says that Zen 5 turns REP MOVS and REP STOS into streaming stores by itself once the string is at least as large as the L3 cache (Section 2.13.6).

VMOVNTDQ stores 16 or 32 bytes with VEX and 16, 32 or 64 bytes with EVEX, without masking, each aligned to its size; Zen 5 ran all five forms. Intel’s entry also says VEX.L must be 0, which its own VEX.256 form contradicts.

In the optimization guide

What the optimization guide says about MOVNTDQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Non-temporal stores and fences: Non-temporal stores skip reading the line and write around the caches through write-combining buffers, with weak ordering.
Non-temporal stores and fences: Non-temporal stores reach full bandwidth only when they write whole 64-byte lines, and the cores have 8 to 12 write-combining buffers for them.

Forms

Every encoding of MOVNTDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVNTDQ m128, xmm` MOVNTDQ_MEMdq_XMMdq	`66 0F E7 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each doubleword is copied to the same place.

Result doubleword i is doubleword i of xmm2. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

mem.write(xmm2.read())

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVNTDQ m128, xmm`
`m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

All forms: aligned memory operand; non-temporal hint; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Aligned, and best in whole lines#

From C#

Zen 5 and the wider forms#