MOVNTDQA instruction (SSE4.1)

MOVNTDQA is the one load among the non-temporal moves: where MOVNTDQ and MOVNTI store around the caches, it reads 16 bytes into an XMM register with a hint that the data should not stay cached. Its address must be a multiple of 16, or it raises #GP, like MOVDQA.

Made for write-combining memory

Intel’s manual applies the hint to write-combining (WC) memory, such as a graphics card’s frame buffer mapped into a process. Ordinary loads from WC memory are not cached, so each one goes to the device. A MOVNTDQA there may fetch the whole 64-byte line into a small buffer beside the caches, and further MOVNTDQAs from the same line take their 16 bytes from that buffer; four of them read a line with one transfer. Intel’s optimization manual names this the streaming load and finds it much faster than other ways of reading WC memory (Section 9.4.4). The buffer can be dropped at any time, and other loads or stores to the line, or reading the same 16 bytes twice, make that likely: a program reads each piece once, with MOVNTDQA only.

On ordinary write-back memory, Intel’s manual lets a processor ignore the hint and run a plain aligned load, or use it to evict less. AMD’s manual describes the load as a WC read without that condition. For data in write-back memory that will be used once, PREFETCHNTA is the hint both vendors document.

Both manuals call for MFENCE where MOVNTDQA must be ordered with other reads, for example before reading a buffer that a device has just written.

The wider forms

VMOVNTDQA loads 16 or 32 bytes with VEX (the 32-byte form needs AVX2) and 16, 32 or 64 bytes with EVEX, without masking; each needs an address aligned to its size. The legacy form keeps bits 128 and up of the register, the VEX and EVEX forms clear them, as Zen 5’s recorded cases show.

From C

_mm_stream_load_si128(p) needs SSE4.1, and _mm256_stream_load_si256(p) AVX2: without the flag, GCC 14 and Clang 23 reject the call. Clang also emits MOVNTDQA for __builtin_nontemporal_load on a 16-byte vector, but a plain MOV for it on a long, since there is no non-temporal load of a general register. AMD’s Zen 5 guide lists MOVNTDQA as a single macro-op, with two per cycle.

Forms

Every encoding of MOVNTDQA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVNTDQA xmm, m128` MOVNTDQA_XMMdq_MEMdq	`66 0F 38 2A /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each doubleword is copied to the same place.

Result doubleword i is doubleword i of m128. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(mem.read())
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVNTDQA xmm, m128`
`xmm`	explicit	write
`m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

All forms: aligned memory operand; non-temporal hint; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVNTDQA, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_stream_load_si128` `__m128i _mm_stream_load_si128(const void *__V)`	`MOVNTDQA xmm, m128` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Made for write-combining memory#

The wider forms#

From C#