MOVNTI instruction (SSE2)

MOVNTI stores a 32-bit or 64-bit general-purpose register to memory with a hint that the data will not be read again soon. Instead of fetching the line into the cache and writing it there, the processor collects the bytes in a write-combining buffer and sends whole lines to memory, leaving the caches to data that will be used. It is the integer sibling of MOVNTDQ and MOVNTPS, and unlike them it has no alignment rule: Zen 5 stored a quadword at an address 4 bytes past an 8-byte boundary. There are no 8-bit or 16-bit forms.

Weakly ordered

On write-back memory, ordinary stores become visible in program order. Streaming stores do not: Intel’s optimization manual describes them as combined, collapsed when they hit the same bytes, and unordered with each other and with other loads and stores (Section 9.4.1). Before another thread or a device may read the data, the writer needs SFENCE, which both vendors name for this, or MFENCE; AMD’s Zen 5 guide says that both empty the write-combining buffers (Table 9). A plain store of a ready flag after a loop of MOVNTIs, with no fence between, may be seen before the data. Memory that is uncacheable or write-protected overrides the hint, and the store behaves as an ordinary one of that type.

From C

_mm_stream_si32(p, v) and _mm_stream_si64(p, v) compile to MOVNTI in GCC 14 and Clang 23 at -O2 with no extra flag, since SSE2 is part of x86-64; Clang’s __builtin_nontemporal_store(v, p) on a long does too. Neither compiler adds a fence of its own: a fill loop gets its SFENCE only from an _mm_sfence() in the source.

When it pays

Both optimization guides tie the gain to whole lines. Intel’s says streaming stores raise bandwidth when all 64 bytes of a line are written one after the other, with no read for ownership (Section 9.4.1.2). AMD’s Zen 5 guide warns that a partly written buffer may stay open for a long time, and advises starting long streams on a 64-byte boundary; it can combine writes to twelve lines at once (Sections 2.13.4 and 2.13.5). Its instruction table lists MOVNTI as microcoded, where MOVNTDQ, which writes 16 bytes at a time, is a single macro-op.

In the optimization guide

What the optimization guide says about MOVNTI, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Non-temporal stores and fences: Non-temporal stores skip reading the line and write around the caches through write-combining buffers, with weak ordering.
Non-temporal stores and fences: Non-temporal stores reach full bandwidth only when they write whole 64-byte lines, and the cores have 8 to 12 write-combining buffers for them.

Bulldozer to Excavator

Loads, stores and caches: Streaming stores such as MOVNTI go through four 64-byte write-combining buffers.

Zen and Zen+

Loads, stores and caches: Streaming stores such as MOVNTI fill 64-byte write-combining buffers, of which eight lines can be open, seven of them for one thread: streams written whole and aligned to 64 bytes, and few at a time, go fastest.

Zen 2

Loads, stores and caches: Streaming stores such as MOVNTI fill 64-byte write-combining buffers, of which eight lines can be open, seven of them for one thread: streams written whole and aligned to 64 bytes, and few at a time, go fastest.

Forms

Every encoding of MOVNTI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVNTI m32, r32` MOVNTI_MEMd_GPR32	`NP 0F C3 /r`	SSE2
`MOVNTI m64, r64` 64-bit mode only MOVNTI_MEMq_GPR64	`REX.W 0F C3 /r`	SSE2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src)                  # with a hint not to keep the line in the
                                 # caches; weakly ordered with other stores
                                 # until an SFENCE or MFENCE

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVNTI m32, r32` `MOVNTI m64, r64` 64-bit mode only
`m32/64`	explicit	write
`r32/64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: non-temporal hint; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVNTI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_stream_si32` `void _mm_stream_si32(void *__p, int __a)`	`MOVNTI m32, r32` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Weakly ordered#

From C#

When it pays#