MOVNTPD instruction (SSE2)

MOVNTPD stores the 16 bytes of an XMM register, read as two doubles, to memory aligned to 16 bytes with a non-temporal hint. It came with SSE2 and is MOVNTPS with a 66 prefix: the bits stored are the same, and so are the weak ordering, the alignment fault and the gain from whole 64-byte lines that MOVNTPS and MOVNTDQ describe. A loop of these stores still needs an SFENCE before another thread or a device may rely on the data. On Zen 5, the one recorded case stored its 16 bytes at an aligned address and left the rest of the buffer as it was.

What the double name changes

Nothing in the store. In our builds at -O2 for the x86-64 baseline and for -march=x86-64-v2, the name follows the compiler:

GCC 14 compiles _mm_stream_pd to MOVNTPD, on its own and in a fill loop, as it compiles _mm_stream_si128 to MOVNTDQ.
Clang 23 compiles the same intrinsic, alone, to MOVNTPS, a byte shorter. In a loop that fills memory with one double broadcast with MOVDDUP at x86-64-v2, it writes MOVNTPD instead, matching the instruction on doubles that made the value; at the baseline, where MOVLHPS makes it, it stays with MOVNTPS.

AMD’s entries for MOVNTPD and MOVNTPS both tell software to fence MOVNTDQ, the instruction of a neighboring entry, where Intel’s name their own instructions; the rule is the same for every streaming store. VMOVNTPD is the VEX and EVEX form, storing 16, 32 or 64 bytes, each aligned to its size.

In the optimization guide

What the optimization guide says about MOVNTPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Non-temporal stores and fences: Non-temporal stores skip reading the line and write around the caches through write-combining buffers, with weak ordering.
Non-temporal stores and fences: Non-temporal stores reach full bandwidth only when they write whole 64-byte lines, and the cores have 8 to 12 write-combining buffers for them.

Forms

Every encoding of MOVNTPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVNTPD m128, xmm` MOVNTPD_MEMdq_XMMpd	`66 0F 2B /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each double is copied to the same place.

Result double i is double i of xmm2. Result doubles 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

mem.write(xmm2.read())

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVNTPD m128, xmm`
`m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

All forms: aligned memory operand; non-temporal hint; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

What the double name changes#