MOVNTPS instruction (SSE)

MOVNTPS stores the 16 bytes of an XMM register to memory aligned to 16 bytes, with a hint that the data will not be read again soon: the processor combines such stores into whole lines and writes them around the caches. It belongs to the family that MOVNTI and MOVNTDQ describe, with the same weak ordering, which needs an SFENCE before another thread is told the data is ready, and the same rule that the memory type can override the hint. Only a store form exists, and only for an aligned address: a misaligned one raises #GP, and AMD’s misaligned SSE mode does not change that.

The first streaming store for XMM registers

MOVNTPS came with SSE, before SSE2 added MOVNTDQ and MOVNTPD, and having no prefix it is the shortest of the three, which store the same 16 bytes. Intel’s optimization manual shows the full-line rule with it: four MOVNTPS stores filling a 64-byte line go out in one write, while three leave a partly written line that needs several (Section 3.6.11, Examples 3-47 and 3-48). On Zen 5, the recorded case wrote its 16 bytes and left the next 16 of the buffer untouched.

In our builds at -O2 for the x86-64 baseline:

_mm_stream_ps compiles to MOVNTPS in GCC 14 and Clang 23, and a fill loop of it gets an SFENCE only from an _mm_sfence() in the source.
Clang also emits MOVNTPS for _mm_stream_si128 and _mm_stream_pd, and for its __builtin_nontemporal_store of a 16-byte vector of floats or doubles. GCC compiles the two intrinsics to MOVNTDQ and MOVNTPD, and GCC 14 has no such builtin.

VMOVNTPS is the VEX and EVEX form, storing 16, 32 or 64 bytes, each aligned to its size.

In the optimization guide

What the optimization guide says about MOVNTPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Non-temporal stores and fences: Non-temporal stores skip reading the line and write around the caches through write-combining buffers, with weak ordering.
Non-temporal stores and fences: Non-temporal stores reach full bandwidth only when they write whole 64-byte lines, and the cores have 8 to 12 write-combining buffers for them.

Forms

Every encoding of MOVNTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVNTPS m128, xmm` MOVNTPS_MEMdq_XMMps	`NP 0F 2B /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each single is copied to the same place.

Result single i is single i of xmm2. Result singles 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

mem.write(xmm2.read())

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVNTPS m128, xmm`
`m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_1

Attributes

What else XED records about the forms. How to read.

All forms: aligned memory operand; non-temporal hint; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVNTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_stream_ps` `void _mm_stream_ps(void *__p, __m128 __a)`	`MOVNTPS m128, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

The first streaming store for XMM registers#