x86-64.net

Instruction

MOVNTSD

Stores the low double of an XMM register to memory with a non-temporal hint; SSE4a.

An AMD extension: Intel processors do not have this instruction.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVNTSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVNTSD m64, xmm MOVNTSD_MEMq_XMMqF2 0F 2B /rSSE4A

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm64, xmm
Piledriver, Jaguar3 / 1FPU1
Zen, Zen 28 / 1FPU2
Zen 3, Zen 41 / 1FP45 FPSt LSU Store

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low quadword of xmm2 goes to m64.
MOVNTSD: the low elementm64 receives quadword 0 of xmm2: a0.01xmm2aa0m64

m64 receives quadword 0 of xmm2: a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

mem.q[0] = xmm2.q[0]

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
MOVNTSD m64, xmm
m64explicitwrite
xmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms
non-temporal hint

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVNTSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_stream_sd void _mm_stream_sd(void *__p, __m128d __a)

MOVNTSD m64, xmm Legacy -msse4a

MOVNTSD m64, xmm Legacy -msse4a -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE4a

SSE4A
CPUID.80000001H:ECX[6] SSE4A

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More SSE4a instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit, 256-Bit, and 512-Bit Media Instructions (26568, rev. 3.27, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.